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Design Verification Emulation, Hardware

River AI· Personal AI Hardware
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Hybrid (Austin, TX or Palo Alto, CA)$200k - $420kFull-timePosted 3w ago

About the role

Emulation-focused design verification engineer driving IP/SoC verification on emulation platforms, translating architectural definitions into emulation workloads, coordinating with DV teams, and providing emulation signoff and tooling/infrastructure to support emulation workflows.

Responsibilities

  • Verification Strategy & Planning: Translate IP and SoC verification plans into execution strategies, mapping tests to simulation, simulation acceleration, or emulator-hosted verification based on runtime, fidelity, and debug needs. Define emulation workload goals and run acceptance criteria with DV block ownersEmulation Models: Build and maintain models and test components for simulation acceleration and emulator-hosted verification flows, balancing fidelity, performance, and debug visibility.
  • Emulation Infrastructure: Develop and improve platform bring-up, compile, mapping, runtime, regression, and debug flows.
  • Testbench and Workload Development: Adapt or develop test environments, transactors, stimulus, and software-driven workloads that run effectively on emulation platforms.
  • Emulation Closure and Signoff: Track workload execution and failures, review results with DV block owners, and help close emulation-specific gaps. Provide emulation signoff as an input to overall IP and SoC verification signoff.
  • Emulation Debug and Collaboration: Triage emulation compile, runtime, and test failures; use traces, waveforms, and platform diagnostics to isolate design, model, testbench, or infrastructure issues; partner with RTL and DV block owners to resolve them.
  • Agentic AI for Emulation: Build and apply agentic workflows across workload planning, model and test preparation, platform setup, run orchestration, failure triage, result analysis, and closure reporting, improving engineering throughput while keeping results traceable and reviewable by DV owners.
  • Automation and Scripting: Build and maintain scripts and tools using Python, Tcl, Bash, or similar languages to improve platform usability, regression throughput, and results visibility.

Qualifications

  • Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, and 5+ years of industry experience.
  • Hands-on experience with platforms such as Cadence Palladium/Protium, Synopsys ZeBu/HAPS, or comparable systems, including bring-up, model integration, compilation, execution, and debug.
  • Experience building or adapting models and test environments for simulation acceleration, emulator-hosted verification, or both.
  • Strong understanding of verification planning, regression strategy, and verification closure, with the ability to translate DV goals into emulation workload and run criteria.
  • Experience verifying complex IP or SoCs, with an understanding of how verification needs change from block-level to system-level testing.
  • Proficiency in SystemVerilog, C/C++, and scripting languages such as Python, Tcl, or Bash.
  • Ability to assess which tests and workloads are effective on emulation platforms, including tradeoffs among runtime, fidelity, observability, and debug.
  • A collaborative mindset and a bias for action when working across design, verification, software, and infrastructure teams.

Skills

Required:Verification strategy and planningEmulation platforms and toolingModeling and test environment developmentSystemVerilog, C/C++, scripting

Benefits

  • River AI offers generous health, dental, and vision benefits, unlimited PTO, and relocation support as needed.
Last updated Sep 30, 2026. Interested? Apply on the company site.
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