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Lead Full-chip STA and timing signoff Engineer

AMD· Engineering
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Hybrid (Bangalore)Full-timePosted 3w ago

About the role

Experienced Full-Chip SoC Timing Lead in ASIC/SoC design implementation and timing closure responsible for leading full-chip timing activities from synthesis through place-and-route, signoff, and tapeout for complex SoCs in advanced technology nodes. Requires deep STA expertise, timing constraints, MMMC flows, SI/crosstalk analysis, ECO closure, and cross-functional collaboration.

Responsibilities

  • Lead full-chip timing closure for complex SoC/ASIC designs across all modes and corners.
  • Own and drive timing signoff from synthesis to final tapeout.
  • Develop, validate, and maintain timing constraints including SDC for full-chip and block-level integration.
  • Perform and review static timing analysis (STA) for setup, hold, recovery, removal, clock gating, and async paths.
  • Drive MMMC timing methodology and ensure robust timing convergence across PVT corners.
  • Work closely with physical design teams on floorplanning, placement, CTS, routing, and post-route timing optimization.
  • Analyze and resolve timing violations related to datapath, clock path, cross-talk, noise, OCV/AOCV/POCV, derates, and variation effects.
  • Lead timing ECO strategies and execute closure with minimal impact to power, area, and performance.
  • Collaborate with RTL/design teams to identify architectural or logic changes required for timing improvement.
  • Coordinate with IP/block owners for timing budgeting, interface timing closure, and hierarchical timing signoff.
  • Ensure signoff quality using industry-standard tools and methodologies.
  • Drive correlation between implementation timing and signoff timing.
  • Lead tapeout readiness reviews and provide timing risk assessment to program leadership.
  • Mentor junior engineers and define best practices for timing methodology and closure.

Qualifications

  • Bachelor’s or Master’s degree in Electronics / Electrical Engineering / VLSI / Microelectronics / Computer Engineering.
  • 12+ years of hands-on experience in ASIC/SoC timing analysis and timing closure.
  • Strong expertise in full-chip STA and timing signoff for large-scale SoCs.
  • Proven experience in advanced technology nodes (such as 7nm, 5nm, 3nm or similar).
  • Strong knowledge of synthesis, place-and-route, extraction, and signoff flows.
  • Experience with timing budgeting and hierarchical/full-chip integration.
  • Solid understanding of clocking architecture, CDC implications, and timing exception handling.
  • Ability to debug complex timing issues and drive closure under aggressive schedule targets.
  • Strong communication, stakeholder management, and leadership skills.

Skills

Required:Full-chip STATiming signoffSynthesis to place-and-routeSDC timing constraintsCross-functional collaboration
Nice to have:MMMC timing methodology

Benefits

  • Benefits offered are described: AMD benefits at a glance.
Last updated Oct 1, 2026. Interested? Apply on the company site.
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