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FCT PD lead

AMD· Engineering
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BangaloreFull-timePosted 3w ago

About the role

Responsible for developing, validating, and maintaining timing constraints and driving full-chip timing convergence for complex SoCs. Own SDC methodology, timing signoff quality, cross-domain timing closure, and collaborate with RTL, Architecture, Tile PnR, Clocking, DFT, and Full-Chip teams to achieve timing signoff targets across all project milestones.

Responsibilities

  • Develop, validate, and maintain block, subsystem, and SoC-level timing constraints (SDC).
  • Perform comprehensive timing analysis and closure for full-chip and partition-level designs.
  • Analyze setup, hold, SI, OCV, AOCV, POCV, CDC-related, and mode-specific timing violations.
  • Drive timing convergence across multiple corners, modes, and milestone releases.
  • Debug timing issues originating from RTL, constraints, clock architecture, physical implementation, and ECO changes.
  • Own timing signoff readiness and ensure timing quality across all project deliverables.
  • Collaborate with Tile PnR, Clocking, DFT, Integration, and RTL teams to resolve critical timing bottlenecks.
  • Develop timing automation, QoR dashboards, and methodology improvements to improve closure efficiency.
  • Support customer timing reviews, signoff audits, and tapeout readiness activities.
  • Mentor junior engineers and provide technical guidance on timing methodologies and best practices.

Qualifications

  • Bachelor's or Master's degree in Electrical Engineering, Electronics, VLSI, Computer Engineering, or related field.
  • 7 to 10 years of experience in STA, Timing Closure, Constraints Development, or Physical Design.
  • Strong understanding of STA concepts including setup, hold, recovery, removal, SI, OCV, AOCV, and POCV.
  • Hands-on experience developing and validating SDC constraints.
  • Proficiency with Synopsys PrimeTime and timing signoff methodologies.
  • Strong understanding of clocking architectures, timing exceptions, and CDC interactions.
  • Experience debugging timing violations and driving closure across multiple corners and modes.
  • Proficiency in Tcl, Python, Perl, or Shell scripting.
  • Strong analytical, problem-solving, and communication skills.

Skills

Required:Timing constraints (SDC) developmentSTA and timing signoffPrimeTime (and related tools)Clocking architecturesScripting

Benefits

  • Benefits offered are described: AMD benefits at a glance.
Last updated Oct 15, 2026. Interested? Apply on the company site.
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