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Physical Design Engineer

AMD· Engineering
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Hybrid (Markham, ON)CA$155.2k - CA$232.8kFull-timePosted 3w ago

About the role

Tile Place & Route (PnR) Lead for complex SoC designs at advanced process nodes, responsible for physical implementation, strategy, execution, and mentorship across multiple programs and teams at AMD.

Responsibilities

  • Lead physical implementation of complex SoC tiles from floorplan through tapeout
  • Drive overall Tile PnR strategy including floorplanning, placement, CTS, routing, timing closure, congestion management, IR/EM closure, and signoff readiness
  • Define implementation methodologies and best practices to improve PPA, scalability, and design quality
  • Drive technical decisions impacting schedule, product quality, and silicon success
  • Lead root-cause analysis and resolution of complex implementation challenges
  • Own execution planning, milestones, risk management, and quality metrics for critical IPs and SoC tiles
  • Coordinate activities across Design, Timing, CAD, Methodology, Full Chip Floorplan, Power, and Verification teams
  • Drive closure on schedule-critical and tapeout-critical issues
  • Provide regular status updates to technical and management leadership
  • Mentor and develop Tile PnR engineers across multiple experience levels
  • Conduct technical reviews and provide implementation guidance
  • Lead training and knowledge-sharing initiatives across the organization
  • Drive adoption of new implementation methodologies, automation, and AI-enabled design solutions
  • Influence future physical design flows and tool direction
  • Partner with CAD teams to improve productivity, scalability, and design predictability

Qualifications

  • BS/MS in Electrical Engineering, Computer Engineering, or related field
  • Industry experience in physical design
  • Demonstrated technical leadership across multiple projects or product families
  • Multiple successful tape-outs at advanced technology nodes
  • Proven experience leading critical tiles or IPs
  • Recognized expert in Tile PnR and physical implementation
  • Experience leading globally distributed engineering teams
  • Expertise in congestion analysis, timing architecture, power optimization, and PPA improvement
  • Experience with AI-assisted implementation methodologies
  • Familiarity with ICC2, Innovous, Fusion Compiler, PrimeTime, RedHawk/Totem, Calibre, and related implementation flows
  • Working knowledge of IREM (strong plus)

Skills

Required:Tile PnRExecution planningLeadership and mentorship

Benefits

  • AMD benefits at a glance
Last updated Oct 22, 2026. Interested? Apply on the company site.
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