Senior STA Design Engineer
BangaloreFull-timePosted 3w ago
About the role
Senior STA silicon design engineer responsible for multi-mode/multi-corner timing constraints, SDC quality, and timing closure for sub-chip/subsystem or full-chip designs. Requires TCL scripting, EDA tool experience, and strong understanding of timing signoff, DFT, and STA flows.
Responsibilities
- Responsible for the development of complex multi-mode / multi-corner timing constraints that are compatible for RTL and signoff
- Ensuring constraints quality (SDC) using industry tools like Fishtail , GCA
- Drive the pre-route timing checks and QoR clean up to eliminate SDC issues and ensure a quality handoff for STA checks
- Requires a mix of SDC knowledge, EDA timing tool competence and Tcl based scripting capability (in both EDA environment and standalone Linux Tcl shell scripts)
- Responsible for Timing closure of one or multiple sub chip/subsystem OR Full chip.
- Ensuring Subsystem/full chip level Interface timing closure along DRV closure
- Generating timing ECO using tools DMSA/Tweaker.
Qualifications
- Bachelors or Masters degree in computer engineering/Electrical Engineering
Skills
Required:SDC (Synopsys Constraints)ECL scripting (Tcl)Timing closure
Benefits
- Benefits offered are described: AMD benefits at a glance.
Last updated Oct 1, 2026. Interested? Apply on the company site.
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