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Lead IP Verification Engineer

AMD· Engineering
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San Jose, CA$200k - $300kFull-timePosted 3w ago

About the role

Senior verification engineer in the AECG Group focusing on front-end design verification for FPGA/ASIC IP, collaborating with cross-functional teams to ensure first-pass silicon success for PCIe and CXL-based IP solutions.

Responsibilities

  • Architect and implement IP or subsystem-level UVM verification environments, including monitors, scoreboards, checkers, and reusable verification components.
  • Collaborate with architects, hardware designers, and firmware teams to define and verify new PCIe, CXL, and high-speed connectivity features.
  • Develop comprehensive verification plans that address feature interactions, hardware/software integration, performance requirements, and system-level use cases.
  • Develop directed and constrained-random tests, execute regressions, and debug failures to ensure high functional coverage and design quality.
  • Drive verification automation, methodology improvements, and adoption of AI-assisted tools to improve development efficiency and productivity.

Qualifications

  • ASIC/IP verification experience using UVM methodology.
  • Strong expertise in SystemVerilog, Verilog, object-oriented programming, and UVM-based verification environments.
  • Experience verifying high-speed protocols such as PCIe, CXL, Ethernet, PCIe Gen6, or 400G Ethernet.
  • Proficiency in scripting and automation using Python, Perl, or similar languages.
  • Experience working across the ASIC/FPGA development lifecycle from planning through tape-out.
  • Exposure to performance verification, simulation optimization, acceleration technologies, HLS tools, or verification efficiency improvements.
  • Technical leadership, mentoring experience, and strong communication skills within geographically distributed teams.
  • Knowledge of computer architecture, system-level design concepts, and emerging AI-driven verification methodologies is a plus.

Skills

Required:UVMSystemVerilogHigh-speed protocols (PCIe, CXL, Ethernet)Python/Perl scriptingASIC/FPGA development lifecycle

Benefits

  • Benefits offered are described: AMD benefits at a glance.
Last updated Oct 8, 2026. Interested? Apply on the company site.
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