Physical Design Engineer
MARKHAM, CanadaCA$105.6k - CA$158.4kFull-timePosted 3w ago
About the role
Role focused on driving PPA improvements for AMD's next-generation graphics processor IP, partnering with RTL, Physical Design, Methodology, and CAD teams from concept to tape-out to deliver best-in-class performance, power, and area.
Responsibilities
- Lead engineer driving PPA improvements for critical graphics blocks, and serves as main point of contact from Physical Design to RTL teams.
- Study block microarchitecture and data flow to determine optimal memory placement & Synthesis/P&R Recipes.
- Work with RTL design to understand upcoming feature changes and resolve potential bottlenecks for frequency, LOL and timing issues early in the project cycle.
- Collaborate with RTL designers to explore additional opportunities for area and power savings.
- Partner with Methodology and CAD teams to optimize tools/flows for achieving best in class PPA.
- Deliver best known recipes to PD tile owners for achieving Performance, Power and Area targets.
- Analyze stdcell library offerings and work with library team to evaluate PPA impact/benefit from different standard cell offerings.
Qualifications
- Bachelors or Masters degree in computer engineering/Electrical Engineering
Skills
Required:PPA optimization
Nice to have:RTL to GDSII ASIC flowVerilogTiming analysis
Benefits
- Benefits described are at a glance on AMD benefits page.
Last updated Oct 15, 2026. Interested? Apply on the company site.
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