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Lead Physical Design Engineer

AMD· Engineering
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Santa Clara, CA$210.4k - $315.6kFull-timePosted 3w ago

About the role

Lead and contribute to advanced-node physical design for complex ASIC and SoC products, driving implementation, timing closure, signoff, and design optimization across block, subsystem, and chip-level designs in AMD’s AI/ HPC silicon initiatives.

Responsibilities

  • Lead physical design activities across block, subsystem, and chip-level implementations.
  • Drive timing closure, signoff readiness, and PPA optimization for advanced-node designs.
  • Develop and enhance physical design methodologies, design flows, and automation solutions.
  • Perform static timing analysis, variation-aware timing analysis, and clock-tree optimization.
  • Define and execute engineering change (ECO) strategies throughout implementation and signoff.
  • Support formal verification, physical verification, and tapeout preparation activities.
  • Analyze design data and trends to improve design quality, predictability, and efficiency.
  • Collaborate with cross-functional engineering teams to achieve successful silicon delivery.
  • Contribute to AI-assisted and machine learning-driven design optimization initiatives.
  • Troubleshoot complex implementation challenges and develop scalable technical solutions.

Qualifications

  • Bachelor's or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field preferred.

Skills

Required:Physical design executionBlock/subsystem/chip-level designStatic timing analysisECO methodologies
Nice to have:Industry toolsTiming/power/signoff toolsAdvanced-node semiconductor designScripting & automationAutomation & design flowsData analysis / ML workflowsData technologies

Benefits

  • Benefits offered are described: AMD benefits at a glance.
Last updated Oct 22, 2026. Interested? Apply on the company site.
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