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SerDes Circuit Design Engineer

Apple· Hardware
Apply on company site
Austin, TXFull-timePosted 3w ago

About the role

Analog Mixed-Signal designer role focused on high-speed SerDes IP development for Apple’s SOCs, delivering best-in-class high-performance transceivers and partnering with cross-functional teams to define, implement, model, test, and deliver IPs for 100+ Gbps NRZ/PAM applications.

Responsibilities

  • Develop high-performance and high-speed AMS circuits used in SerDes PHY (Rx, CDR, Tx, bias generator, high-speed clock generation and low-jitter distribution, phase interpolator, DLL, VCO, LDO)
  • Evaluate different circuit topologies to meet product requirements
  • Lead discussions with cross-functional teams to create and drive block-level specifications, mixed-signal implementations and behavioral modeling
  • Work with SOC teams to deliver IP views and ensure quality standards
  • Communicate progress and drive new implementations/concepts with peers and management
  • Drive lab testing, debugging and data analysis to validate designs
  • Supervise layout and collaborate with packaging, board design, DFT, ESD, and other teams as needed
  • Mentor and guide junior engineers in developing circuit components for TX, RX, PLL, etc.

Qualifications

  • BS and a minimum of 10 years relevant industry experience
  • Deep understanding of analog mixed-signal design with experience in high-speed serial links
  • Experience designing AMS blocks (Bandgap, biasing circuits, LDOs, amplifiers, comparators, switched-cap circuits, ADCs, DACs, Oscillators, Filters)
  • Understanding of mismatch mitigation, linearity, stability, low-power and low-noise techniques
  • Understanding of digitally assisted analog design concepts (e.g., background calibrations, LMS adaptive loops)
  • Proven track record with system/architecture teams to drive block-level and IP requirements for high-speed IO in 100+ Gbps NRZ/PAM
  • Experience with high-speed digital circuits (serializer/deserializer, counters, dividers)
  • Experience with Tx/Rx equalization techniques (CTLE, DFE, de-emphasis) for 100+ Gbps NRZ/PAM
  • Experience with EQ adaptation methods to improve PPA
  • Solid understanding of CDR architectures
  • Experience in AMS circuit modeling and performance evaluation (SystemVerilog, Matlab, Python, VerilogAMS)
  • Hands-on lab testing, debugging and data analysis
  • Hands-on experience in advanced CMOS/FinFET technologies
  • Experience with AMS IC development from definition to high-volume production including layout supervision, bench evaluation, correlation, and characterization
  • Knowledge of timing closure tools (e.g., Nanotime, Primetime)
  • IP delivery and quality process knowledge
  • Knowledge of high-speed SerDes protocols (PCIe, USB, DP, MPHY) is highly desirable
  • Scripting and automation skills are highly desirable

Skills

Required:Analog mixed-signal designCircuit blocks (Bandgap, biasing, LDO, amplifiers, comparators, switched-cap circuits, ADCs, DACs, oscillators, filters)Mismatch mitigation, linearity, stability, low-noise techniquesDigitally assisted analog design (calibrations, LMS loops)System-level collaborationHigh-speed IO in 100+ Gbps NRZ/PAMTx/Rx equalization (CTLE, DFE, de-emphasis)CDR architecturesAMS circuit modeling and evaluation (SystemVerilog, Matlab, Python, VerilogAMS)Lab testing, debugging, data analysisCMOS/FinFET technologiesAMS IC development lifecycleTiming closure tools (Nanotime, Primetime)IP delivery and quality checks
Nice to have:High-speed SerDes protocols (PCIe, USB, DP, MPHY)Scripting and automation

Benefits

  • Competitive compensation
  • Comprehensive health and wellness benefits
  • 401(k) or equivalent with company matching
  • Paid time off and family leave
  • Employee stock purchase plan
  • Tuition assistance
  • Career development opportunities
  • Diversity and inclusion programs
Last updated Oct 2, 2026. Interested? Apply on the company site.

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