Senior Digital IC Engineer — RTL Design & Verification
About the role
Senior Digital IC Engineer responsible for owning a substantial digital subsystem in a mixed-signal ASIC, including RTL design, verification, and implementation handoff. Remote contract role with potential for full-time, location-based in the US.
Responsibilities
- Requirements and interfaces: clarify behavior with firmware and analog engineers, document interfaces, derive implementation requirements and verification tests.
- Digital design: develop and refine RTL for digital control and configuration logic, articulate design tradeoffs, assess integration risks.
- Verification: create a verification plan tied to requirements, build self-checking testbenches and regressions, use coverage to identify gaps and drive fixes.
- Implementation handoff: manage lint, clock/reset-domain crossing analysis, synthesis, timing constraints, static timing analysis, and provide reproducible build-and-test flow and integration documentation.
Qualifications
- Personal ownership of digital or mixed-signal ASIC work through RTL design, synthesis and tapeout, with validation of silicon.
- Strong SystemVerilog RTL design and self-checking verification skills.
- Hands-on experience with synthesis, static timing analysis and timing constraints.
- Good judgment around metastability, reset behavior and asynchronous interfaces.
- Experience resolving hardware–firmware or mixed-signal interface questions with engineers from other disciplines.
- Ability to work independently and communicate decisions, risks and verification results clearly.
- Power-management ICs, mixed-signal integration and silicon bring-up experience are particularly relevant.
- FPGA experience is valuable alongside ASIC experience, but does not replace tapeout and working-silicon requirement.
Skills
About Visibl Semiconductors
AI-Native Broadcom as a Service
Visibl is an AI platform that turns compute into chip design capacity. As chips grow more complex, adding engineers yields diminishing returns — coordination costs rise while progress slows. The bottleneck is no longer ideas, but execution throughput. Visibl turns compute into a teammate. Our platform ingests the full design context (code, specs, scripts, tool outputs) to decode ambiguous tool feedback into actionable steps. We validate changes and package decisions for review, resulting in safer changes, shorter iteration cycles, and fewer late surprises on the path to tapeout.