Standard Cell Design Enablement Lead
MarkhamCA$128kFull-timePosted 2w ago
About the role
Lead role focused on developing and supporting Standard Cell Libraries and in-house process characterization structures, ensuring performance, power, area, and cost targets across advanced CMOS technologies. Collaboration with design, layout, verification teams and external vendor partners to manage library release, QA, and issues.
Responsibilities
- Communication with external standard cell library vendor regarding schedules, requirements, SOW (statement of work)
- Driving communication with our external standard cell library vendors and internal customers related to library release schedules and contents, questions and issues.
- Oversight of download, build, release, QA of libraries.
- Coordinate the effort to download, build, release and QA vendor standard cell libraries, as well as driving discussion for internally developed cells from our customers.
- Addressing requests and issues for standard cells.
Qualifications
- MSEE/MSCS in related field
- Standard cell design and layout analysis.
- Proficiency in industry-standard EDA tools for PDK, DRC, LVS, Virtuoso, PEX, capacitance modeling, and EMIR and reliability analysis.
- Experience with IR Drop analysis techniques and tools.
- Schematic and layout entry, physical and logical verification, extraction, timing characterization using industry standard EDA tools in advanced semiconductor processes, with Unix shell environments and scripting (Perl, Python).
- Experience with SPICE simulation and familiarity with industry-standard modeling techniques.
- Proficiency in Unix shell environments, Perl, and Python scripting.
Skills
Required:Standard cell design and layout analysisEDA tools (SNPS/CDNS/Siemens)Schematic and layout entry, verification, extraction, timing characterizationUnix shell, Perl, Python
Nice to have:IR Drop analysisSPICE simulation
Benefits
- AMD benefits at a glance
Last updated Oct 22, 2026. Interested? Apply on the company site.
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