CPU Architecture and RTL Design Engineer
Hybrid (Dublin or Cork, Ireland)Full-timePosted 2w ago
About the role
CPU Architect/RTL Design Engineer focused on CPL microarchitecture, clocking, reset and power integration for AMD's next-generation CPUs. Role involves RTL design, collaboration across design teams, and delivering designs from concept to tapeout.
Responsibilities
- Collaborate with a dedicated team of engineers to define and implement CPL microarchitecture for AMD CPUs.
- Reliably deliver a design from concept through tapeout by innovating through complex and challenging requirements.
- Drive design closure gaining experience with Static Timing, CDC/Gate CDC, and Static Power analysis.
- Identify customer challenges and insert a compelling AMD value proposition to address challenges.
- Make technical contributions and innovations that enable high performance, high frequency, and power efficiency on caches, fabrics, and interfaces of our server, desktop, and laptop CPUs.
Qualifications
- Proficiency with Verilog HDL, Clock/Power Domain Crossing concepts, and Power Management concepts.
- Understanding of modern CPU architecture - prior experience designing shared cache or last level cache and related IPs a plus.
- Eagerness to learn and grow as a CPL design engineer.
- Collaborate effectively towards the success of the project by working closely with logic design, physical design and verification teammates across the wider organization.
- Demonstrate a responsive track record of engaging with a diverse set of teams and across a broad set of technical areas to facilitate design delivery.
- Bachelors or Masters degree in computer engineering/Electrical Engineering
Skills
Required:Verilog HDLClock/Power Domain CrossingPower ManagementCollaboration / teamwork
Nice to have:CPU Architecture
Benefits
- Benefits offered are described: AMD benefits at a glance.
Last updated Oct 22, 2026. Interested? Apply on the company site.
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