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Lead Server Performance Architect

AMD· Engineering
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BangaloreFull-timePosted 2w ago

About the role

Senior technical leader responsible for architecting, validating, and optimizing server performance across full chip simulation, emulation, and pre-silicon validation for AMD-based servers. Focuses on IPC, latency, throughput, and power efficiency; drives cross-functional collaboration and strategic direction for performance verification programs in server CPUs.

Responsibilities

  • Lead and mentor a high-performing team of performance verification engineers.
  • Foster a culture of innovation, technical rigor, and continuous improvement.
  • Provide strategic direction across multiple concurrent verification programs.
  • Define and execute the performance verification strategy for high-performance x86 server CPU.
  • Collaborate with architecture, u-arch, RTL, performance modeling, firmware, and software teams to define and validate performance KPIs.
  • Ensure timely delivery of simulation/emulation results, and optimization feedback loops.
  • Develop and execute performance verification plans targeting IPC, latency, throughput, and power efficiency.
  • Debug performance outliers through Performance Monitoring Counters (PMC).
  • Drive correlation between RTL and performance models, ensuring architectural intent is met.
  • Analyze performance bottlenecks using simulation, emulation, and silicon data.
  • Build and maintain scalable, modular performance verification infrastructure.
  • Lead emulation-based performance setup and debug, enabling early performance validation.
  • Integrate performance regression, profiling, and analysis flows using industry-standard and custom tools.
  • Collaborate with compiler and OS teams to align software stack with hardware performance goals.
  • Drive AI/ML-based infrastructure to automate performance analysis, anomaly detection, and efficiency improvements.
  • Leverage data-driven techniques to optimize verification coverage and reduce debug cycles.
  • Partner with x86 architecture, RTL design, physical design, and software teams to ensure performance targets are met.
  • Influence design decisions through data-backed performance insights.
  • Align verification goals with business and product roadmaps.
  • Communicate performance status, risks, and trade-offs to executive leadership and stakeholders.
  • Stay current with trends in CPU architecture, performance modeling, and verification technologies.
  • Evaluate and adopt emerging tools and techniques to maintain a competitive edge.

Qualifications

  • 15+ years of industry experience with performance modeling and simulation tools (e.g., cycle-accurate simulators, emulators) with strong background in CPU microarchitecture, performance analysis, and system-level performance verification.
  • Proven leadership in managing large, cross-functional engineering teams.
  • Familiarity with PMC DV, latency and throughput validation, emulation platforms, and performance debug flows.
  • Deep understanding of x86 ISA, microarchitecture, and performance metrics.
  • Experience in developing performance test suites, performance triage tools, and simulation/emulation infrastructure.
  • Expertise in performance analysis tools, correlation techniques, and workload optimization.
  • Strong analytical and problem-solving skills with a data-driven mindset.
  • Deep knowledge of modern out-of-order CPU cores, memory subsystems, and performance modeling is a plus.
  • Experience with ML/AI techniques/frameworks for performance triage, infrastructure automation and prediction is a plus.
  • Exposure to HPC, virtualization, or server-class CPUs.
  • Background in hardware/software co-design and performance-aware compiler optimizations.
  • Familiarity with pre-silicon and post-silicon debug methodologies.

Skills

Required:Performance verification leadershipCPU microarchitecturePerformance modeling & simulationRTL familiarity and SOC bringup

Benefits

  • AMD benefits at a glance
Last updated Oct 8, 2026. Interested? Apply on the company site.
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