ASIC Physical Design & Implementation Lead
BangaloreFull-timePosted 2w ago
About the role
Lead physical design for next generation ASICs within the AECG organization, coordinating RTL-to-GDS2 flows and end-to-end physical implementation to meet engineering, business, and customer requirements.
Responsibilities
- Implementing RTL to GDS2 flow
- Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR, Formal Equivalence
- Deft at Handling different PNR tools - Synopsys Fusion Compiler, ICC2, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk, Cadence Genus, Innovus
- Full Chip Level Floor planning, Bus / Pin Planning, feed-thru planning, Clock Tree Synthesis, Placement, Optimization, Routing, Parasitic Extraction, Static Timing Analysis, Physical Verification and Sign Off
- Identify complex technical problems, break them down, summarize multiple possible solutions
- Drive and hands-on flow development and scripting
Qualifications
- BS or MS degree in Electrical Engineering or Computer Science
- 12 years of experience in physical design role leading to an understanding of RTL to GDS development
- 12+ years of professional experience in physical design, preferably with high performance designs
Skills
Required:RTL to GDS2 flowFloorplanningPower/Clock planningSynthesisTiming ClosurePhysical VerificationParasitic Extraction1st-tier EDA toolsScripting/AutomationTeam collaboration
Benefits
- Benefits offered are described: AMD benefits at a glance
Last updated Oct 22, 2026. Interested? Apply on the company site.
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