Lead Full Chip Floorplan Design Engineer
Bangalore, IndiaFull-timePosted 2w ago
About the role
Full-Chip Floorplan Engineer for ASIC/SoC development within AMD's AECG SSD Custom Silicon group, focused on physical implementation planning, floorplanning, power/interconnect/thermal strategies, and cross-functional collaboration to achieve PPA targets across complex SoCs.
Responsibilities
- Full-Chip Floorplanning: Develop and own top-level SoC floorplan architecture; Define chip aspect ratio, die size, partitioning strategy, and hierarchy planning; Perform macro placement and optimization for timing, congestion, power, and thermal considerations; Drive floorplan refinement through design milestones; Define floorplan topology for large-scale SoCs containing multiple subsystems, hard IPs, memories, and third-party IPs.
- Physical Architecture Planning: Develop and optimize power domain strategy, voltage island planning, power grid architecture, isolation and retention planning, feedthrough strategy, repeater insertion strategy, boundary and channel planning.
- IO and Package Planning: Define chip-level IO placement strategy; Collaborate with package teams on bump map optimization; Drive chip-package co-design activities; Optimize high-speed interface placement (PCIe, SerDes, C2C, DDR, Ethernet, etc.).
- Interconnect & Timing Planning: Develop timing-driven floorplans; Define physical partitions and timing boundaries; Establish timing budgeting methodology across subsystems; Plan clock distribution architecture and clock-domain placement.
- Congestion, Power & Thermal Optimization: Identify congestion hotspots and implement mitigation strategies; Drive early power estimation and thermal-aware floorplanning; Optimize placement for PPA convergence; Support EMIR-aware floorplan planning.
- Cross-Functional Collaboration: Work with Architecture, RTL, Physical Design, DFT, Packaging, Power methodology, and Verification teams; Review subsystem floorplans and ensure full-chip integration readiness.
- Methodology and Automation: Develop scripts and automation for floorplan generation and analysis; Drive methodology improvements and best practices; Enable scalable planning methodologies for next-generation SoCs.
Qualifications
- 12+ years of ASIC/SoC Physical Design experience with strong expertise in Full-Chip Floorplanning
- Bachelor's or Master's degree in Computer Engineering or Electrical Engineering
Skills
Required:Full-Chip FloorplanningPhysical Architecture PlanningIO & Package PlanningInterconnect & Timing PlanningCongestion, Power & Thermal OptimizationCross-Functional Collaboration
Nice to have:Automation & Scripting
Benefits
- Benefits offered are described: AMD benefits at a glance.
Last updated Oct 22, 2026. Interested? Apply on the company site.
About AMD
together we advance_AI
AMD delivers leadership high-performance and adaptive computing solutions to advance data center AI, AI PCs, intelligent edge devices, gaming, & beyond.
AIData CenterHigh-Performance ComputingGamingEdge Devices
More open roles at AMD
- System Thermal Design Staff Engineer5d agoPenang, Malaysia · Engineering
- PD Engineer5d agoHybrid (Bangalore) · Engineering
- PD Engineer5d agoBangalore · Engineering
- Low-Power & CDC Verification Engineer5d agoSanta Clara, California · Engineering
- Technical Program Manager5d agoShanghai · Engineering