Synthesis STA silicon design Engineer
HyderabadFull-timePosted 2w ago
About the role
The role focuses on leading front-end implementation of IP Subsystems and their physical partitions, owning synthesis, LEC, CLP, prelayout STA, and postlayout STA/Timing closure, and coordinating with design and PNR teams.
Responsibilities
- Responsible for front end implementation of IPs which includes synthesis, LEC, CLP, prelayout STA and postlayout STA/Timing closure
- Collaborate with designer and PNR teams to achieve closure.
- Understand duration required, plan and execute as per schedule.
- Complete quality delivery for synthesis and timing closure.
- Debug and resolve technical issues
Qualifications
- Bachelors with 7 years of experience or Masters degree with 5 years of experience in Electrical Engineering
Skills
Required:SynthesisLECCLPTiming Closure
Nice to have:PNR (Place and Route)Scripting and Automation
Benefits
- Benefits offered are described: AMD benefits at a glance
Last updated Oct 22, 2026. Interested? Apply on the company site.
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