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Full Chip Timing Lead

AMD· Engineering
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HyderabadFull-timePosted 2w ago

About the role

MTS Full chip STA (FCT) Silicon Design Engineer responsible for SoC Full Chip Timing closure and SDC validation, collaborating with PD, CAD, and methodology teams to achieve first pass silicon success.

Responsibilities

  • Owns Full chip Timing Closure
  • Drive new improvement in closure
  • Analysis of data and feedback to PD execution team
  • SDC analysis and feedback
  • Work with PnR engineer for timing convergence
  • Drive the common STA methodology in the business unit
  • Work and collaborate with different business units, CAD and central methodology team to drive the requirement
  • Automation to refine and improve design signoff requirement and dashboarding
  • Ability to organize and present complex technical information in a crisp and concise manner.
  • Interact with other PPA (equivalent) teams internal to AMD
  • Identify best practices across AMD and industry to update and improve flow/project settings
  • To increase the competitiveness of each stage in AMD design flow
  • Ability to work with multi-level functional teams across various geographies.
  • Highly organized, strong affinity for automation and prioritization.

Qualifications

  • Bachelors with 7 years of experience or Masters degree with 5 years experience in timing

Skills

Required:Timing closureSDC coding and debuggingScriptingPnR signoff
Nice to have:AutomationML in physical design
Last updated Oct 8, 2026. Interested? Apply on the company site.
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