Timing Constraint Development Engineer
Hybrid (Hyderabad, India)Full-timePosted 2w ago
About the role
MTS Timing constraint development ENGINEER role focused on planning and developing timing constraints for IPs, subsystems, or full chips, including SDC development, generation, verification, promotion/demotion, and equivalence checking. May expand to synthesis, LEC, CLP, prelayout/postlayout timing in pursuit of timing closure, coordinating with design and PNR teams, and mentoring team members.
Responsibilities
- Own constraints, SDC development for IPs, SS and SoCs, including SDC generation, verification, promotion, demotion and equivalence using third party or self-built tools
- Prior experience with Lint, CDC and RTL & Netlist based static checks is a plus
- Collaborate with designer and PNR teams to achieve closure
- Understand duration required, plan and execute as per schedule
- Complete quality delivery for synthesis and timing closure
- Debug and resolve technical issues
Qualifications
- Bachelors with 7 years of experience or Masters degree with 5 years of experience in Electrical Engineering
Skills
Required:Timing constraintsSDC
Nice to have:Synthesis
Last updated Oct 8, 2026. Interested? Apply on the company site.
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