Lead Verification Engineer
Hyderabad, IndiaFull-timePosted 2w ago
About the role
The focus of this role is to plan, build, and execute the verification of new and existing features for AMD’s graphics processor IP, resulting in no bugs in the final design.
Responsibilities
- Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified
- Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases
- Estimate the time required to write the new feature tests and any required changes to the test environment
- Build the directed and random verification tests
- Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues
- Review functional and code coverage metrics – modify or add tests or constrain random tests to meet the coverage requirements
Qualifications
- Bachelors or Masters degree in computer engineering/Electrical Engineering
- Experience in SOC verification
- Proficient in IP level ASIC verification
- Proficient in debugging firmware and RTL code using simulation tools
- Proficient in using UVM testbenches and working in Linux and Windows environments
- Experienced with Verilog, System Verilog, C, and C++
- Developing UVM based verification frameworks and testbenches, processes and flows
- Automating workflows in a distributed compute environment
- Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process
- Good understanding and hands-on experience in the UVM concepts and SystemVerilog language
- Scripting language experience: Python, Makefile, shell preferred
- Exposure to leadership or mentorship is an asset
Skills
Required:Feature verification planningUVMVerilog/SystemVerilogC/C++
Nice to have:Python
Benefits
- Benefits offered are described: AMD benefits at a glance.
Last updated Oct 22, 2026. Interested? Apply on the company site.
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