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Interconnect Micro-architect/RTL Design Engineer

AMD· Engineering
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Austin, TX$178.4kFull-timePosted 2w ago

About the role

RTL design engineer role within AMD's Infinity Fabric Architecture and RTL team, focusing on coherent interconnects between CPU, GPU, and accelerators, across multiple product families and markets.

Responsibilities

  • Early architectural/performance exploration through micro architectural definition and design.
  • Optimize the design to meet power, performance, area and timing requirements.
  • Write easily readable and synthesizable Verilog RTL.
  • Run some unit level testing to deliver quality code to the Design Verification Team.
  • Create assertions to improve coverage and cover points to analyze coverage of the design.
  • Create well written block level design documentation.
  • Participate in post silicon functional and performance debug and tuning.

Qualifications

  • Proven experience designing logic blocks in CPU, GPU, NOC, or cache designs.
  • Excellent knowledge of Verilog and System Verilog
  • Working knowledge of C, C++ and a scripting language like Perl or Python
  • Strong understanding of digital electronics and high-speed designs(>1GHz).
  • Good understanding of multi-processor coherency, memory ordering, i/o ordering, interrupts, MMU and caches.
  • Good debugging and analytical skills
  • Exposure to Design for Test, understanding of scan concepts and writing DFT friendly RTL
  • Working knowledge of x86 or ARM ISA is a plus.

Skills

Required:VerilogSystemVerilog
Nice to have:C/C++Scripting (Perl/Python)
Last updated Oct 15, 2026. Interested? Apply on the company site.
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