STA/Constraints Engineer
Hybrid (Vancouver, BC)CA$128k - CA$192kFull-timePosted 2w ago
About the role
The STA/Constraints Engineer is responsible for developing FullChip constraints and timing closure, collaborating with cross-functional teams across Physical Design, Timing Analysis, Synthesis, Physical Verification, and Power signoff, and mentoring Design Engineers.
Responsibilities
- Own end-to-end delivery of designs (SOC and Sub-system integration) from timing constraints and timing signoff perspective.
- Work closely with the SOC Architecture team for SOC clocks & STA for statistical timing target goals.
- Understanding clock design requirements and making sure they are correctly set up in SDC.
- Understand timing margins (LVF/SSTA/Variations etc.) on the latest tech nodes and work with timing methodology teams for future and current projects.
- Understand design requirements, timelines and various milestones of a project and deliver FCT closure accordingly.
- Collaborate with CAD and EDA vendors to further strengthen AMD timing closure and constraints methodology.
- Responsible for cdc/lint, timing closure, lower power implementation and netlist quality check with RTL designer and PD team.
- Work on SDC development, STA (Static Timing) analysis, shift left of timing closure, CDC (Clock Domain Crossing).
Qualifications
- Industry experience in STA, constraints and timing signoff.
- Expert user of industry-standard PD tools like SNPS PT/GCA (must) and ICC2/FC (desired).
- Good experience with Perl/TCL/Shell/Python scripting, and Verilog RTL design.
- Excellent presentation and inter-communication skills.
- Experience with Verilog RTL design/implementation and has experience of large digital ASIC project.
- Experience with physical design is a plus.
- Has Synthesis or physical implement experience.
- Experience with lower power design methodology.
- Good English skills on talking, presentation and writing documents.
- Good communication and strong sense of responsibility, task scheduling, and time management.
Skills
Required:STA (Static Timing Analysis)Constraints Development (SDC)Timing ClosurePD Tools (SNPS PT/GCA, ICC2/FC)Scripting (Perl/TCL/Shell/Python)Verilog RTL
Benefits
- Benefits offered are described: AMD benefits at a glance.
Last updated Oct 8, 2026. Interested? Apply on the company site.
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