Principal Memory Subsystem Architect
Georgia$176.6kFull-timePosted 2w ago
About the role
The Memory Standards Architecture team seeks an LPDDR and DRAM Buffer Standards Architect to own AMD’s architecture strategy for low-power DRAM and advanced memory-buffer technologies, lead technical positions, and represent AMD in JEDEC and the memory ecosystem.
Responsibilities
- Own AMD’s multi-generation LPDDR and DRAM-buffer architecture strategy, including adoption plans, priorities, risks, ownership, and business-unit decisions, and serve as the company-wide technical authority for LPDDR devices, registered clock drivers, and advanced DRAM-buffer technologies.
- Develop and maintain AMD technical positions for JEDEC and related standards organizations, advancing standards work through proposals, ballots, technical negotiations, objection resolution, partnerships, and consensus building.
- Define architectural requirements for LPDDR devices, DDR6 registered clock drivers, LPDDR6 in-package buffers, future buffer architectures, and supporting components.
- Establish requirements covering partitioning, topology, interfaces, protocols, command and data behavior, clocking, training, performance, power, telemetry, reliability, security, test, error handling, recovery, and interoperability.
- Coordinate DRAM and buffer architectures with controller, PHY, SoC, package, module, board, firmware, validation, and platform requirements, evaluating tradeoffs among discrete, module-level, in-package, die-integrated, DRAM-integrated, and host-side implementations.
- Deliver implementation requirements and guidance for architecture, SPD, configuration, firmware, authentication, attestation, power, thermal design, packaging, compliance, margining, characterization, robustness, and fault handling.
- Align DRAM vendors and suppliers of buffers, PMICs, regulators, hubs, connectors, and related technologies on roadmaps, qualification plans, interoperability, readiness milestones, and adoption risks.
- Lead cross-functional architecture workgroups, document decisions and ownership, resolve technical tradeoffs, drive closure of standards and implementation dependencies, and provide adopting teams with reusable solutions, specifications, implementation guidance, issue resolution, and launch-readiness support.
Qualifications
- Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field required; master’s degree or PhD preferred.
Skills
Required:LPDDR and DRAM-buffer architectureJEDEC standards participationSystem integration and cross-functional leadership
Benefits
- AMD benefits at a glance
Last updated Oct 15, 2026. Interested? Apply on the company site.
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