Sr DFT/ATPG Engineer–Mixed-Signal IP
Fort Collins, CO$200k - $300kFull-timePosted 2w ago
About the role
The Scan ATPG Engineer will own scan architecture and validation strategy for analog and mixed-signal IP, delivering production-quality test patterns and supporting silicon bring-up and debug. Collaborative, cross-functional role focused on robust, manufacturable DFT solutions for high-quality testing in analog/mixed-signal IP.
Responsibilities
- Define and document scan architectures for analog and mixed-signal IP, considering test coverage, implementation complexity, timing, power, area, and integration requirements.
- Develop and maintain ATPG models for custom digital, analog-interface, and mixed-signal circuitry to enable accurate fault modeling and pattern generation.
- Validate scan-stitched gate-level netlists, including scan-chain connectivity, test-mode controls, clocks, resets, constraints, and cross-domain behavior.
- Analyze, debug, and improve test coverage to achieve appropriate coverage targets across multiple fault models, including stuck-at and transition-delay faults.
- Perform zero-delay and SDF-annotated gate-level simulations of ATPG patterns; identify and resolve simulation failures, timing issues, X-propagation, and model or netlist mismatches.
- Own the generation, validation, documentation, delivery, and lifecycle management of production test patterns.
- Partner with product and test engineering teams to support pattern deployment, silicon bring-up, yield learning, failure analysis, and post-silicon debug.
- Collaborate with cross-functional teams to identify and resolve testability issues and contribute to improvements in architecture, methodology, automation, and quality.
Qualifications
- Experience with scan design, ATPG, fault simulation, coverage analysis, and pattern validation for complex IP or SoC designs.
- Experience applying DFT methodologies to analog and mixed-signal IP, including modeling custom circuitry and interfaces for ATPG.
- Experience with industry-standard ATPG, gate-level simulation, waveform-debug, and DFT verification tools.
- Knowledge of multiple fault models, such as stuck-at, transition-delay, cell-aware, bridging, or comparable advanced defect-oriented models.
- Experience identifying and resolving scan-chain, netlist, constraint, clocking, reset, timing, and X-propagation issues.
- Knowledge of zero-delay and SDF-annotated simulation flows and production pattern formats.
- Experience supporting silicon bring-up, production test deployment, yield learning, post-silicon failure analysis, or closely related activities.
- Programming or scripting experience with Python, Perl, Tcl, or comparable languages for flow development, data analysis, or automation.
- Demonstrated ability to lead technical work, collaborate across functions, build alignment around technical decisions, and communicate technical concepts to a range of stakeholders.
Skills
Required:Scan designATPGFault simulationDFT tools
Nice to have:Python/Perl/Tcl
Benefits
- AMD benefits at a glance (link provided in posting)
Last updated Oct 15, 2026. Interested? Apply on the company site.
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