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FE integration & STA IP Lead- Advanced Technologies Group

Apple· Hardware
Apply on company site
Hybrid (Herzliya)full-timePosted 2w ago

About the role

IP timing lead role focusing on pre-silicon development, constraints definition, and timing convergence to achieve first silicon IP tape-out. Responsible for IP-level netlist generation, timing constraints from synthesis to sign-off, and cross-functional collaboration across RTL, CAD, and Physical Design to optimize flows and ensure sign-off quality.

Responsibilities

  • Own the entire IP-level netlist generation and timing convergence journey from synthesis to sign-off.
  • Drive synthesis, UPF power intent, scan insertion, and external IP integration.
  • Architect timing constraints for standard and complex custom designs to ensure sign-off quality from day one.
  • Collaborate with RTL designers to understand design intent and clock architecture, CAD teams to shape and optimize flows, and Physical Design engineers to achieve timing sign-off.
  • Proactively identify and resolve timing challenges to accelerate convergence and improve method efficiency.

Qualifications

  • Bsc/Msc in Electrical Engineering
  • 5+ years of experience in the field
  • At least 2+ years of experience in writing ASIC timing constraints and achieving timing closure
  • Expertise in STA tools (Primetime) and flow generation
  • Knowledge of the ASIC design timing closure flow and methodology
  • Understanding of timing corners/modes
  • Familiarity with process variations and signal integrity-related issues
  • Hands-on experience in generating and managing timing/SDC constraints, proficient in scripting languages (Tcl and Perl)
  • Knowledge of synthesis, DFT, and backend-related methodologies and tools
  • Strong communication skills to interact with various groups

Skills

Required:ASIC timing constraintsTiming closurePrimetimeScriptingSynthesis
Nice to have:DFT
Last updated Oct 9, 2026. Interested? Apply on the company site.

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