PMU Digital Design Verification Intern (m/f/d)
Apple· Hardware
Hybrid (Nabern)internPosted 2w ago
About the role
Internship in the Silicon Engineering Group focusing on pre-silicon verification of mixed-signal designs for Apple power management units. Collaborates with Digital and Analog Design engineers to enable bug-free first silicon through verification methodology, test plans, environments, and automated flows.
Responsibilities
- Develop verification plans in coordination with design leads and architects
- Build and maintain verification test bench components and environments
- Generate directed and constrained random tests
- Run simulations and debug design and environment issues
- Build functional coverage points, analyze coverage, and improve test environment to target coverage holes
- Craft automated verification flows for block and chip level verification
- Apply knowledge of hardware description languages (VHDL/Verilog), hardware verification languages (SystemVerilog/UVM), and logic simulators to verify complex designs
- Work with other block and core level engineers to ensure a flawless verification flow
- Work with Assertion Based Verification
Qualifications
- Bachelor’s in EE or related field, or equivalent work experience
- Excellent communication and interpersonal skills, combined with the ability to collaborate
- Ability to work well on a team, take ownership and motivate self and others
- Fluent English skills (written and verbal)
- Good knowledge of SystemVerilog and UVM
- Experience with Python, Perl or TCL
- Good knowledge of Object Oriented Programming
- Available for 6 months or more
- Experience developing scalable and portable test-benches
- Good understanding of digital design and basic knowledge of mixed signal verification
Skills
Required:SystemVerilogUVMPythonVerilog/VHDLObject Oriented Programming
Nice to have:Test bench developmentMixed-signal verification
Benefits
- Not specified in description
Last updated Oct 9, 2026. Interested? Apply on the company site.
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