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Experienced AMS Design Verification Engineer

Apple· Hardware
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Londonfull-timePosted 2w ago

About the role

Design Verification Engineer in Apple’s Advanced Technology group in London, responsible for pre-silicon verification of mixed-signal designs, developing self-checking verification environments, and collaborating with Analog and Digital Design teams to ensure bug-free tape-outs.

Responsibilities

  • Definition and design of Self-checking verification environments for multi-layer systems using the SystemVerilog UVM library.
  • Concept discussions, verification strategy definition and execution of verification tasks to ensure bug-free tape-outs.
  • Development of verification environments, coding of test scenarios and assertions.
  • Collaboration with Analog and Digital Design engineers.
  • Deliveries of tests for design and test engineering teams.
  • Gate-level verification (power and timing).
  • Lab bring-up support.
  • Research and innovations to improve verification techniques and tools for mixed-signal systems.

Qualifications

  • System Verilog test-bench language and UVM (Universal Verification Methodology)
  • Hands-on experience with constrained random verification environments
  • Basic design background in support of verification results analysis
  • Knowledge of Object Oriented Programming (OOP)
  • Master’s degree or PhD in Electrical/Computer Engineering or proven industrial experience/degree equivalent
  • Experience in AI/ML is desired
  • Hands-on experience with Assertion Based Verification
  • Familiarity with system design using C++, Python or Verilog
  • Familiarity with FPGA emulation platforms
  • Proficiency in English language

Skills

Required:SystemVerilogUVMConstrained random verification
Nice to have:OOPC++PythonVerilog
Last updated Oct 9, 2026. Interested? Apply on the company site.

About Apple

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