AMS STA / Timing Engineer (m/f/d)
Apple· Hardware
Hybrid (Munich, Germany)Full-timePosted 2w ago
About the role
Static Timing Engineer focused on timing closure for ASIC SoC, collaborating with RTL designers, CAD, and Physical Design to develop and sign-off timing constraints for full chip, IP, and block levels.
Responsibilities
- Timing sign-off, STA and sign-off flow development
- Ownership of full chip, IP, and block level timing constraints from synthesis to sign-off
- Developing timing constraints for regular and custom timing requirements
- Collaborating with RTL designers to understand design intent and clock structure
- Collaborating with CAD to develop timing flows
- Collaborating with Physical Design to close and sign-off timing
- Proposing and implementing timing verification plans to enable timing closure and address pessimism/fallouts in timing analysis
Qualifications
- Bachelor or Master’s degree in Electrical Engineering or relevant years of experience
- Relevant years of experience in writing ASIC timing constraints and timing closure
- Validated experience in STA tools (PrimeTime) and flow, knowledge of timing corners/modes, process variations & signal integrity issues
- Hands-on experience in timing/SDC constraints generation and management
- Proficiency in scripting languages (Tcl and Perl)
- Knowledge of synthesis, DFT and backend methodologies and tools
- Excellent communication and interpersonal skills; ability to collaborate with diverse teams
- Ability to work well in an international team, take responsibility, perform under strict deadlines, balance priorities
- Proficiency in English
Skills
Required:ASIC timing constraintsPrimetimeScripting (Tcl, Perl)
Nice to have:Synthesis, DFT backend
Benefits
- Apple Equal Opportunity Employer with inclusion and diversity commitments
- Reasonable accommodation for applicants with disabilities during application/interview process
- Accessibility and workplace inclusion initiatives
Last updated Oct 23, 2026. Interested? Apply on the company site.
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