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Experienced AMS Design Verification Engineer (m/f/d)

Apple· Hardware
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MunichFull-timePosted 2w ago

About the role

Design Verification Engineer in Apple’s Advanced Technology group in Munich, focusing on bug-free pre-silicon verification for mixed-signal designs, including environment construction, test scenarios, assertions, and collaboration with Analog and Digital Design teams to enable first silicon success.

Responsibilities

  • Definition and design of Self-checking verification environments for multi-layer systems using the SystemVerilog UVM library.
  • Concept discussions, verification strategy definition and execution of the verification tasks to ensure bug-free tape-outs.
  • Developing verification environments and test scenarios and assertions.
  • Deliveries of tests for design and test engineering teams.
  • Gate-level verification (power and timing).
  • Lab bring-up support.
  • Performance-based analysis and power-related analysis and scenario design for early power estimation.
  • Research and innovation to improve verification techniques and tools for mixed-signal systems.

Qualifications

  • Knowledge of System Verilog test-bench language and UVM (Universal Verification Methodology)
  • Hands-on experience with constrained random verification environments
  • Basic design background in support of verification results analysis
  • Knowledge of Object Oriented Programming (OOP)
  • Proficiency in English language
  • Master’s degree or PhD in Electrical/Computer Engineering or proven industrial experience/degree equivalent
  • Experience in AI/ML is desired
  • Hands-on experience with Assertion-Based Verification
  • Familiarity with system design using C++, Python or Verilog
  • Familiarity with FPGA emulation platforms

Skills

Required:SystemVerilogUVM (Universal Verification Methodology)Constrained Random VerificationOOPEnglish proficiency
Nice to have:C++/Python/VerilogFPGA emulation platforms
Last updated Oct 9, 2026. Interested? Apply on the company site.

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