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SerDes Circuit Design Engineer

Apple· Hardware
Apply on company site
Waltham, MA$165.8k - $292.4kFull-timePosted 2w ago

About the role

Analog Mixed-Signal designer for high-speed SerDes team developing IP for Apple’s SOC. Role involves designing and verifying high-performance AMS blocks for SerDes PHY, leading cross-functional discussions, and delivering IPs that meet quality standards with a focus on power, performance, and area (PPA).

Responsibilities

  • Develop high-performance, high-speed AMS circuits used in SerDes PHY (e.g., Rx, CDR, Tx, bias generator, high-speed clock generation, low-jitter distribution, phase interpolator, DLL, VCO, LDO)
  • Evaluate circuit topologies to meet product requirements
  • Lead discussions with cross-functional teams (architecture, SIPI, packaging, board design, DFT, ESD) to define block-level specifications and behavioral models
  • Collaborate with SOC teams to deliver IP views and ensure quality standards
  • Drive new implementations/concepts; communicate progress and ideas with peers/management
  • Drive lab testing, debugging and data analysis
  • Work with analog mixed-signal design teams to create, execute and drive state-of-the-art IPs
  • Guide junior engineers and collaborate with large teams to develop TX/RX/PLL components for high-speed IO
  • Understand and leverage digitally assisted analog design concepts and LMS-based adaptive loops

Qualifications

  • BS and a minimum of 10 years relevant industry experience
  • Deep understanding of analog mixed-signal design with experience in high-speed serial links
  • Experience designing analog blocks including Bandgap, biasing circuits, LDOs, amplifiers, comparators, switched-cap circuits, ADCs, DACs, Oscillators, Filters
  • Understanding of mismatch mitigation, linearity, stability, low-power and low-noise techniques
  • Understanding of digitally assisted analog design concepts (e.g., background calibrations, LMS based adaptive loops)
  • Proven track record with system/architecture teams to drive block-level and IP requirements for high-speed IO in 100+ Gbps NRZ and PAM applications
  • Proven track record of guiding junior engineers on TX/RX/PLL components for high-speed IO
  • Experience with high-speed digital circuits (serializer/deserializer, counters, dividers) and digital design concepts
  • Experience with TX/RX equalization techniques (CTLE, DFE, de-emphasis) for 100+ Gbps NRZ/PAM
  • Experience with EQ adaptation methods to improve PPA
  • Solid understanding of CDR architectures
  • Experience in Analog Mixed Signal circuit modeling/evaluation (SystemVerilog, Matlab, Python, VerilogAMS)
  • Hands-on lab testing, debugging and data analysis
  • Hands-on experience with advanced CMOS/FinFET technologies
  • Experience with AMS IC development from definition to high-volume production (layout supervision, bench eval, correlation, characterization)
  • Timing closure concepts and tools (Nanotime, Primetime)
  • IP delivery and quality checks
  • Knowledge of high-speed SerDes protocols (PCIe, USB, DP, MPHY) is highly desired
  • Scripting and automation skills are highly desirable

Skills

Required:Analog mixed-signal designHigh-speed SerDes block design (Rx, Tx, CDR, PLL, VCO, LDO)Digital design for high-speed IOTX/RX equalization techniques (CTLE, DFE, de-emphasis)SystemVerilog/VerilogAMSMatlab/PythonLab testing and debug

Benefits

  • Comprehensive medical and dental coverage
  • Retirement benefits
  • Discounted products and free services
  • Educational expense reimbursement including tuition
  • Discretionary bonuses or commission potential
  • Relocation assistance where applicable
Last updated Oct 9, 2026. Interested? Apply on the company site.

About Apple

Discover the innovative world of Apple and shop everything iPhone, iPad, Apple Watch, Mac, and Apple TV, plus explore accessories, entertainment, and expert device support.

Discover the innovative world of Apple and shop everything iPhone, iPad, Apple Watch, Mac, and Apple TV, plus explore accessories, entertainment, and expert device support.

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