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Lead Formal Verification Engineer

AMD· Engineering
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Hybrid (Austin, TX; Orlando, FL; San Diego, CA)$200k - $300kFull-timePosted 1w ago

About the role

Lead Formal Verification Engineer at AMD to drive formal verification strategy, methodology, and adoption across next-generation graphics and GPU IP; roles include technical leadership, collaboration with architecture, design, and verification teams, and expanding formal verification across the development lifecycle.

Responsibilities

  • Define and drive formal verification strategy, methodology, and technical roadmap for graphics IP.
  • Lead formal verification efforts for complex GPU and processor designs while improving coverage, quality, and scalability.
  • Develop and deploy advanced verification techniques to solve challenging convergence and verification problems.
  • Drive development of reusable infrastructure, automation, and workflows that improve verification productivity.
  • Partner with architecture, design, and verification teams to influence design quality and verification planning.
  • Research and evaluate emerging formal verification applications in areas such as security, safety, low power, and architectural verification.

Qualifications

  • In-depth knowledge of formal verification methodologies, algorithms, proof engines, and practical applications across complex digital designs.
  • Proven expertise in SystemVerilog Assertions (SVA), property development, and abstract model creation.
  • Expert-level experience with formal verification tools such as JasperGold, VC Formal, Murphi, theorem provers, or similar EDA solutions.
  • Demonstrated success delivering high-quality verification for large-scale processor architectures, including GPU, CPU, AI accelerator, or other high-performance compute designs; strong understanding of computer architecture and graphics pipelines preferred.
  • Proven experience developing formal verification infrastructure supporting applications such as functional property verification, datapath verification, equivalence checking, security verification, or related use cases.
  • Experience solving challenging formal convergence problems and scaling formal verification through advanced techniques such as induction, abstraction, reduction, decomposition, and related approaches.

Skills

Required:Formal verification methodologiesSystemVerilog Assertions (SVA)Formal verification tools

Benefits

  • Benefits offered are described: AMD benefits at a glance.
Last updated Oct 22, 2026. Interested? Apply on the company site.
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