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Senior Staff Product Application Engineer-Memory Subsystems

AMD· Engineering
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San Jose, CA$193.2k - $289.8kFull-timePosted 1w ago

About the role

Technical lead for memory subsystem issues across AMD’s silicon portfolio, spanning DDR/LPDDR, memory controller, NoC and physical interface. Acts as the primary technical contact for escalated memory cases from design-in to production, driving root-cause analysis, fixes, and documentation, and influencing product roadmaps with cross-functional leadership.

Responsibilities

  • Own escalated customer support issues for memory, from early design-in and bring-up through production support. Partner with key customers to root-cause system memory failures such as intermittent errors, calibration and training failures, and margin and boot issues. Attribute each correctly across DRAM, board, controller IP, calibration firmware and silicon, and drive the fix to closure.
  • Be the authority on DDR and LPDDR, covering JEDEC standards, device behavior, module topologies, ranks, widths and supported data rates. Know how traffic reaches the controller across the Network-on-Chip, including QoS, arbitration, and bandwidth and latency budgeting.
  • Author the customer-facing memory documentation, including product guides, user guides, datasheets, answer records, tutorials and layout guidance, and publish resolutions internally and externally.
  • Review memory and NoC architecture and design specifications for next-generation silicon, identifying gaps, inconsistencies and design bugs, and proposing fixes. Evaluate and validate its memory RAS features.
  • Perform DRAM SI/PI and timing measurements. Apply PCB layout and routing knowledge for DDR and LPDDR to assess customer designs and define the layout guidance we publish. Support IBIS/IBIS-AMI models and channel simulation.
  • Create experiments and tooling that catch memory health issues before they are reported. Write targeted memory tests in C to stress and characterize specific failure modes on real hardware.
  • Translate system-level challenges into product and roadmap decisions on supported configurations, data rates, feature scope and documentation accuracy. Drive teams across IP, firmware, tools, signal integrity, validation and quality without direct authority, for feature enablement, optimization and characterization.
  • Use AI to surface design gaps, summarize and correlate large test and log datasets, and drive productivity in debug, automation and documentation.

Qualifications

  • Extensive hands-on experience with memory subsystems in an applications, architecture, design, or validation role, built across multiple DRAM generations and product cycles.
  • Expertise across DDR and LPDDR generations (DDR4/DDR5, LPDDR4/4X/5/5X/6), with fluency in JEDEC specs and module variants (UDIMM, SODIMM, RDIMM, LRDIMM, CUDIMM). HBМ experience is a plus.
  • Excellent technical writing with a track record of authoring customer-facing documentation such as product guides, user guides, datasheets, answer records and tutorials.
  • Deep knowledge of DRAM, memory controller and PHY architecture: command scheduling and arbitration, address mapping and decode, calibration and training, DQS gating and delay-line behavior, termination and drive strength, voltage and temperature tracking, page policy, and RAS feature validation.
  • Working knowledge of Network-on-Chip interconnect and bandwidth/latency budgeting.
  • Proven root cause analysis of system-level memory failures with hands-on lab debug, including oscilloscope, logic/protocol analyzers, and JTAG-based debugging.
  • Experience with memory SI/PI measurement, timing analysis, eye/margin analysis and channel simulation using IBIS/IBIS-AMI; practical PCB layout knowledge.
  • Experience working with strategic customers in technical/architecture-facing roles, mentoring and leading technical reviews without direct authority.
  • Demonstrated use of AI in engineering workflows to identify design gaps and boost productivity.
  • Strong C skills for writing targeted memory tests; ability to read SystemVerilog/Verilog RTL to identify implementation bugs.

Skills

Required:Memory subsystem expertiseTechnical writingRoot-cause analysisC programming
Nice to have:SystemVerilog/Verilog RTL reading

Benefits

  • AMD benefits at a glance (link provided in posting)
Last updated Oct 22, 2026. Interested? Apply on the company site.
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