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Sr. Manager - RTL Design Manager

AMD· Engineering
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Hybrid (Markham, ON)CA$167.3k - CA$250.9kFull-timePosted 1w ago

About the role

Senior engineering leadership role in the Security IP (SECIP) Design team focusing on RTL design, microarchitecture, verification, and cross-functional collaboration to deliver RTL IP and subsystems for AMD SoC products.

Responsibilities

  • Define, develop, and maintain RTL-level IP and subsystem functional specifications, and align microarchitecture and design solutions with product requirements in collaboration with SoC, architecture, design, verification, and validation teams.
  • Establish, track, and drive key design metrics and targets by correlating design intent with implementation results and identifying optimization opportunities.
  • Lead and coordinate RTL design activities from specification through integration and project delivery.
  • Collaborate with functional and implementation verification teams to debug and resolve design issues across simulation, formal, emulation, and post-silicon validation environments.
  • Work with corporate methodology and SoC integration teams to adopt and develop traditional and AI-assisted methodologies for microarchitecture development, RTL design, structural analysis, and design validation.
  • Drive the closure of RTL quality metrics, including lint, CDC, RDC, synthesis, low-power verification, and other implementation-related checks.
  • Coordinate resolution of IP integration issues with SoC integration, SoC verification, firmware, and post-silicon validation teams.
  • Partner with project managers, architects, and technical leads to ensure delivery of IP milestones while meeting schedule, quality, power, performance, and area objectives.
  • Mentor, coach, and develop engineers while fostering a culture of technical excellence, innovation, collaboration, and accountability.

Qualifications

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related discipline.
  • Master's degree or Ph.D. preferred.

Skills

Required:RTL designVerilog/SystemVerilogScriptingCross-functional leadership
Nice to have:IP/RTL managementMicroarchitecture & RTL methodologyMP subsystem architectures & datapathAMBA/AXI/AHBASIC design & verification flows

Benefits

  • Benefits offered are described: AMD benefits at a glance (link provided in posting)
Last updated Oct 15, 2026. Interested? Apply on the company site.
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