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Senior IC Layout design Engineer

AMD· Engineering
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San Jose, CA$156.5k - $234.7kFull-timePosted 1w ago

About the role

Senior analog/mixed-signal layout design engineer with supervisory responsibilities in AMD’s SerDes Technology Group, focusing on high-speed SerDes layout in advanced CMOS processes and collaboration across global teams.

Responsibilities

  • Layout design of high speed and high performance SerDes analog mixed signal circuit in accordance to project requirements and specifications
  • Block level physical implementation which includes floor-planning, power distribution network, clock and signal routing, analog and mixed signal transistor level layout
  • Participate in post-layout circuit performance analysis
  • Participate in block/IP/chip level integration activities
  • Estimate realistic schedule, track and report clear progress and status
  • Strong participation in defining layout methodology and flow
  • Driving layout productivity improvement initiatives (i.e: pcell development and automation)
  • Supervision of layout resources (onsite and offsite), assessing and correcting layout quality issues, and providing feedback to design teams.

Qualifications

  • Bachelor degree in EE/CE or IC layout training Certificate with IC Layout working experience.

Skills

Required:Layout designFloor-planning and PDNPost-layout analysisLayout verificationCross-site collaboration
Nice to have:Cadence SKILL / programming

Benefits

  • Benefits offered are described: AMD benefits at a glance
  • AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services.
  • We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
Last updated Oct 22, 2026. Interested? Apply on the company site.
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