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PD Lead

AMD· Engineering
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HyderabadFull-timePosted 1w ago

About the role

PHY‑V Lead role focused on physical verification sign-off, full-chip integration, and packaging interface planning for advanced SoC programs, with leadership across PD, Analog, and Packaging teams to ensure tapeout readiness and sign-off quality.

Responsibilities

  • Drive end-to-end DRC, LVS, ERC, antenna closure at block and full-chip level
  • Define and enforce sign-off methodology and quality criteria
  • Own foundry rule decks, waivers, and risk assessments
  • Deliver sign-off clean GDS for tapeout
  • Lead top-level integration of IPs/macros into SoC
  • Own GDS assembly and hierarchical LVS reconciliation
  • Resolve boundary issues, connectivity mismatches, and integration conflicts
  • Ensure robust integration across internal and third-party IPs
  • Drive RDL planning and bump mapping strategy
  • Define IO escape routing and die–package interface
  • Collaborate with Packaging, SI/PI, and system teams
  • Enable flip-chip / 2.5D / 3D integration readiness
  • Own sign-off checklist, closure tracking, and tapeout readiness
  • Lead tapeout reviews and milestone tracking
  • Drive cross-team closure to meet schedule and quality targets
  • Define and improve physical verification flows (Calibre/ICV/Pegasus)
  • Drive automation (TCL/Python) and runtime optimization
  • Establish best practices for hierarchical and incremental sign-off
  • Lead debug of complex DRC violations and LVS mismatches
  • Drive closure with PD/layout teams
  • Minimize waivers and ensure risk-managed sign-off
  • Lead and mentor PHY‑V engineers
  • Act as primary escalation point for sign-off issues
  • Interface with PD / PnR, Analog/layout, Packaging and foundry teams

Qualifications

  • B.Tech / M.Tech in Electronics / Electrical Engineering
  • 10–15+ years in Physical Design / Physical Verification / SoC Integration
  • Strong expertise in DRC, LVS, ERC, antenna checks
  • Tools: Calibre / ICV / Pegasus
  • Solid understanding of Full PD flow (RTL → GDS → sign-off)
  • Advanced process nodes (7nm and below)

Skills

Required:Physical VerificationSign-off and Tapeout

Benefits

  • Benefits offered are described: AMD benefits at a glance.
Last updated Oct 22, 2026. Interested? Apply on the company site.
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