Memory PHY Principal Design Engineer
Santa Clara, CA$232kFull-timePosted 1w ago
About the role
Senior Memory PHY design engineer role at AMD focused on architecting and developing high-speed memory interface IP (LPDDR/DDR) and leading digital PHY architecture, RTL, and firmware development in collaboration with multiple cross-functional teams.
Responsibilities
- Define product features and capabilities, translate architecture and microarchitecture requirements into technical specifications, and provide technical direction to execution teams.
- Lead Memory PHY digital architecture development from pathfinding and microarchitecture through RTL implementation, verification, and physical realization.
- Architect and implement PHY link-layer functionality in partnership with analog and system architects.
- Drive analog and digital co-design, digital logic development, RTL coding, and firmware integration for high-speed memory interfaces.
- Guide synthesis, static timing analysis, timing closure, power optimization, and physical implementation to achieve power, performance, and area targets.
- Collaborate with architecture, hardware, verification, firmware, and physical design teams to define, implement, and validate new product features.
- Identify complex technical issues and risks across IP and domain boundaries, then drive architectural solutions that meet product requirements.
- Contribute technical knowledge, design guidance, and reusable methodologies across platform and system architecture teams.
- Support post-silicon teams in debugging and resolving functional, performance, and power issues.
- Advance AI-assisted design, verification, debug, and productivity methodologies to improve engineering efficiency, design quality, and time to market.
Qualifications
- Deep expertise in Memory PHY architecture and implementation, including LPDDR, DDR, GDDR, HBM, SerDes, memory controllers, or other high-speed I/O subsystems.
- Expert proficiency in Verilog or SystemVerilog, digital design methodologies, and scripting languages such as Python, Perl, or Tcl.
- Strong experience with mixed-signal integration, clocking architectures, clock-domain and reset-domain crossing methodologies, low-power design, UPF, synthesis, static timing analysis, timing closure, and silicon bring-up.
- Demonstrated expertise in power-management microarchitecture, low-power design, and power optimization across architecture, logic, and circuit levels.
- Experience guiding technical direction across multiple teams and organizations while building consensus among senior stakeholders.
- Proven ability to mentor engineers, share technical knowledge, and strengthen engineering practices across an organization.
- Strong communication and presentation skills, with the ability to collaborate effectively across disciplines, sites, and time zones.
Skills
Required:Memory PHY architectureVerilog/SystemVerilogScripting (Python, Perl, Tcl)
Benefits
- AMD benefits at a glance
Last updated Oct 22, 2026. Interested? Apply on the company site.
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