DFT Integration Lead
Hybrid (Bangalore)Full-timePosted 1w ago
About the role
DFT Design Engineer role within AMD's S3 SoC DFx Team focused on DFT design and integration for advanced silicon, including SCAN, ATPG, MBIST, and BSCAN. Requires end-to-end DFT flow experience, strong scripting skills, and collaboration across RTL, IP teams, and PD.
Responsibilities
- Working closely with the DFT Architecture and the various IP Design teams to align on the DFT requirements and successfully implementing the DFT design
- Design and develop correct by construction DFT design and support DFT verification
- Working closely with the RTL designers, Verification Engineers, and PD team to find creative ways to accelerate the identification of functional defects.
Qualifications
- B.E/B.Tech/M.E/M.Tech in Electrical/Electronics Engineering
- 11+ years’ experience in DFT Design
Skills
Required:ASIC DFTEnd-to-End DFT flow development/creationPerlPythonTCLEDA tools (Tessent, Design Compiler, Spyglass)RTL development (Verilog/SystemVerilog)Unit-level verificationRTL quality checks (Spyglass, CDC, Lint)IP integration into SOCsStatic timing analysis & timing closureDFT pattern & test flow developmentDebug and scriptingCommunication
Nice to have:Low power concepts (clock gating, power gating)Post-silicon bring-up
Benefits
- Benefits offered are described: AMD benefits at a glance.
Last updated Oct 22, 2026. Interested? Apply on the company site.
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