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Sr. Director of Packaging Engineering

AMD· Engineering
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San Jose, CA$269k - $403.4kFull-timePosted 1w ago

About the role

Senior leadership role responsible for strategy, development, and execution of advanced IC packaging technologies across AMD’s silicon portfolio. Leads a global engineering team, shepherds packaging from concept to manufacturing ramps, and partners with product teams and suppliers to meet performance, reliability, cost, and schedule targets.

Responsibilities

  • Champion best practices in design-for-manufacturability, reliability, and cost optimization across the package, SI/PI and thermal/mechanical technology portfolio
  • Lead, mentor, and grow a global team of engineers and technical leads; building organizational depth through development of talent, including specialized SI/PI and thermal/mechanical design expertise
  • Own end-to-end packaging development from concept through new product introduction (NPI) and high-volume manufacturing (HVM), including design rules, qualification, and yield/reliability ramp
  • Direct package-level signal integrity and power integrity co-design strategy, including interconnect/channel modeling, power delivery network (PDN) design, impedance control, and high-speed serial/parallel interface optimization for multi-die and chiplet architectures
  • Own thermal and mechanical package design strategy, including thermal simulation and characterization, warpage control, die/package stress management, and thermal-mechanical co-design for high-power, high-density silicon
  • Participate in strategic relationships with OSAT, substrate, and PWB supply partners, including technology development, qualification, capacity planning, and HVM ramp for next-generation nodes
  • Partner cross-functionally with business units, silicon/product design, marketing, applications, product engineering, operations, and quality to translate product requirements into scalable packaging solutions
  • Drive technology proliferation and standardization initiatives to improve development velocity, technology reuse, manufacturing scalability, and cost competitiveness across the packaging portfolio
  • Represent AMD’s packaging technology strategy in cross-functional and executive reviews, and externally with customers as appropriate
  • Drive innovation in heterogeneous integration, chiplet-based architectures, and high-speed/optoelectronic packaging to support AMD’s multi-die, networking, and accelerator roadmap
  • Establish and monitor engineering budgets, headcount planning, and program schedules for the packaging organization

Qualifications

  • Significant and progressive experience in semiconductor IC packaging engineering, with a track record of advancing from individual contributor/engineering manager into director-level technical leadership
  • Direct experience developing and qualifying packaging solutions for complex digital, mixed-signal, RF, or high-speed silicon
  • Deep, hands-on technical expertise across advanced and standard packaging technologies, such as WLCSP, flip-chip, chip-on-chip, multi-chip module, system-in-package (SiP), 2.5D/3D integration, or chiplet interconnect
  • Demonstrated expertise in package-level signal integrity engineering, including high-speed interconnect modeling/simulation (S-parameters, channel/eye analysis), crosstalk mitigation, and co-design with SerDes/interface teams for die-to-die and die-to-package interconnects
  • Demonstrated expertise in power integrity engineering, including PDN design and analysis, decoupling strategy, IR drop/impedance targets, and co-design with silicon power delivery teams for high-power accelerator and multi-die products
  • Demonstrated expertise in thermal and mechanical package design, including thermal simulation (e.g., FEA/CFD), thermal interface material (TIM) selection, warpage and stress modeling, and package-level reliability under thermal cycling for high-power/high-density applications
  • Proven experience managing OSAT, substrate, and/or PWB supplier partnerships, including technology qualification, capacity planning, and high-volume manufacturing ramp
  • Experience leading global engineering teams, with a track record of hiring, developing, and retaining technical talent
  • Excellent cross-functional leadership and communication skills, with experience partnering across business units, design, applications, operations, and quality, and presenting to executive stakeholders

Skills

Required:Packaging engineering leadershipPackage-level signal integrity

Benefits

  • Benefits offered are described: AMD benefits at a glance
Last updated Oct 22, 2026. Interested? Apply on the company site.
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