Design Verification Lead
Hybrid (Markham, ON)CA$155.2kFull-timePosted 1w ago
About the role
Design Verification Lead in the AECG Group responsible for delivering FPGA/ASIC verification for PCIe, CXL, and high-speed connectivity in next-generation IP solutions. Leads front-end design and integration efforts with architecture, IP design, physical design, firmware, and product engineering to achieve first-pass silicon success.
Responsibilities
- Collaborate with architects, hardware designers, and firmware teams to define and verify new PCIe, CXL, and high-speed connectivity features.
- Develop comprehensive verification plans that address feature interactions, hardware/software integration, performance requirements, and system-level use cases.
- Design and implement IP or subsystem-level UVM verification environments, including monitors, scoreboards, checkers, and reusable verification components.
- Develop directed and constrained-random tests, execute regressions, and debug failures to ensure high functional coverage and design quality.
- Drive verification automation, methodology improvements, and adoption of AI-assisted tools to improve development efficiency and productivity.
Qualifications
- ASIC/IP verification experience using UVM methodology.
- Strong expertise in SystemVerilog, Verilog, object-oriented programming, and UVM-based verification environments.
- Experience verifying high-speed protocols such as PCIe, CXL, Ethernet, PCIe Gen6, or 400G Ethernet.
- Proficiency in scripting and automation using Python, Perl, or similar languages.
- Experience working across the ASIC/FPGA development lifecycle from planning through tape-out.
- Exposure to performance verification, simulation optimization, acceleration technologies, HLS tools, or verification efficiency improvements.
- Technical leadership, mentoring experience, and strong communication skills within geographically distributed teams.
- Knowledge of computer architecture, system-level design concepts, and emerging AI-driven verification methodologies is a plus.
Skills
Required:UVM-based verificationSystemVerilogHigh-speed protocols (PCIe, CXL, Ethernet)Python/Perl scriptingASIC/FPGA lifecycle
Nice to have:Performance verification / acceleration toolsTechnical leadership
Benefits
- AMD benefits at a glance
Last updated Oct 15, 2026. Interested? Apply on the company site.
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