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Early Career - GPU Top Level Physical Design Engineer

Apple· Hardware
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Hybrid (Cambridge)full-timePosted 1w ago

About the role

GPU Top Level Physical Design engineer responsible for implementing complete chip design from netlist to tapeout, with hands-on experience in physical design and large chip integration. Collaborates with front-end RTL team, develops methodologies and PD guidelines, and serves as the focal point for place and route integration at the top level.

Responsibilities

  • Collaborate with FE team to understand RTL and drive physical aspects early in design cycle.
  • Drive innovation with the physical design team by developing methodologies and best known methods for best-in-class GPU design.
  • Develop PD guidelines and checklists, drive execution, and supervise progress.
  • Be the focal point for place and route integration at the top level.
  • Communicate and drive the needs of PD with cross-functional teams to enable back-end design goals for the project.

Qualifications

  • Minimum of BSc/MSc in EE and some relevant experience.
  • Familiar with ASIC integration including Floorplanning, Clock and Power distribution, global signal planning, I/O planning and hard IP integration.
  • Experience integrating IP from both internal and external vendors and ability to specify and drive IP requirements in the physical domain.
  • Experience with Physical Design topics: multiple voltage and clock domains, ESD solutions, and mixed signal block integration.
  • Experience with large subsystem designs (>20M gates) with frequencies in excess of 1GHz applying brand new technologies.
  • Familiar with process-related design issues including Design for Yield and Manufacturability, multi-Vt strategies and thermal management.
  • Proven track record in solving complex PD and cross-functional problems, driving results directly or directing a team of engineers.
  • Understanding of GPU architecture and design units.
  • Experience with hierarchical design approach, top-down design, budgeting, timing and physical convergence.
  • Experience with Floorplanning tools, P&R flows, global timing verification and Physical Design Verification Flows.

Skills

Required:RTL understandingFloorplanningIP integrationPhysical DesignGPU architectureTop-down / hierarchical designFloorplanning tools / P&R / verification
Last updated Oct 16, 2026. Interested? Apply on the company site.

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