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CPU Cache Architect

AMD· Engineering
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Hybrid (Fort Collins, CO)$144.8k - $217.2kFull-timePosted 5d ago

About the role

AMD is seeking an experienced design engineer to advance performance modeling, performance analysis, and microarchitecture development for next-generation cores and caches, based in Fort Collins, CO.

Responsibilities

  • Collaborate with a small, dedicated team of hardware and software engineers to optimize the performance of CPUs, caches, and interconnect.
  • Develop and enhance cycle-accurate core, cache, and SoC (System on a chip) performance simulators.
  • Develop other simulators at different abstraction levels.
  • Use simulators, analytical methods, emulation, and post-silicon observation to develop and evaluate microarchitecture improvements.
  • Develop and improve tools and methodology for performance analysis of workloads.
  • Guide and mentor junior engineers.

Qualifications

  • C++ programming and scripting language capabilities
  • Computer architecture background with industry experience in architecting processors, caches, and interconnect.
  • Familiarity with Digital RTL Design, Verilog HDL. Experience writing and debugging RTL.
  • Experience collaborating effectively towards the success of a project by working closely with a diverse team across disciplines.
  • BS/MS/PhD in EE, CS, CSE (or similar), and expertise in hardware design preferred

Skills

Required:C++Computer Architecture
Nice to have:ScriptingDigital RTL Design / Verilog HDL

Benefits

  • Benefits offered are described: AMD benefits at a glance (link provided in posting)
Last updated Oct 22, 2026. Interested? Apply on the company site.
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