PLL Design/ Integration Sr Staff Engineer
San Jose, CA$200kFull-timePosted 5d ago
About the role
Senior staff design engineer role focused on analog/mixed-signal PLL integration for FPGA products within AMD's AECG Fabric team, leading design, integration, and characterization of PLLs across cutting-edge process nodes and collaborating across clocking, fabric, and software teams.
Responsibilities
- Architect and integrate analog/mixed-signal PLL building blocks (VCOs, charge pumps, dividers, PFDs, Loop Filters), LDO, Phase Interpolator, High Speed Divider into FPGA products across cutting-edge process nodes.
- Lead the integration of different PLL topologies (e.g., integer-N, fractional-N, all-digital/ADPLL) to meet specifications for power, area, jitter, and frequency range at product level.
- Address challenges in advanced node technologies, such as self-heating, electromigration, voltage-controlled oscillator (VCO) linearization and device-level noise optimization for Product level Jitter optimization
- Supervise and verify layouts produced by PD engineers to ensure floor planning, matching, and parasitic minimization using advanced node technologies
- Be responsible for PLL bring up in the lab, conducting performance characterization using state-of-the-art lab equipment
- Conduct comprehensive system-level simulations and validation for PLL IP integration in FPGA environment using Vivado or similar tools/flows.
Qualifications
- Experience in IC design and manufacturing including analog/digital IP integration (e.g., PLLs, LDOs, Phase Interpolators), chip design, silicon processes, and packaging technologies.
- Strong understanding of device physics, reliability, and silicon chip manufacturing.
- Passion for modern adaptive computing architectures and post-silicon validation and characterization.
- Collaborative mindset with effective cross-team communication and strong analytical/problem-solving skills.
Skills
Required:Analog/Mixed-Signal PLL designPLL topology integrationLab bring-up and characterizationSystem-level simulation
Nice to have:Device physics and reliability
Last updated Oct 22, 2026. Interested? Apply on the company site.
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