Silicon Design Engineer
Shanghai, ChinaFull-timePosted 5d ago
About the role
Senior silicon design engineer role focused on fullchip floorplan CAD methodology development and production deployment for large-scale SoC designs, delivering robust, scalable full-chip floorplanning solutions and providing technical leadership across multiple teams at AMD.
Responsibilities
- Own and drive major functions' methodology and flow development for large-scale SoC designs.
- Develop methodologies to identify and optimize repeater and feedthrough requirements based on floorplan, connectivity, timing, hierarchy, and physical constraints.
- Drive complex technical issues to resolution across timing, long-distance interconnect, hierarchy, placement, congestion, and routability.
- Develop robust and scalable CAD automation using Tcl, Python, Perl.
- Drive methodology and flow improvements from concept, prototyping and validation through production deployment.
- Work across Physical Design, Front-End Design/Integration, Timing teams to align requirements and ensure successful methodology integration.
- Provide technical leadership and guidance, conduct technical reviews, and mentor junior engineers.
- Proactively identify methodology gaps, propose solutions, and drive continuous improvements in quality, scalability, runtime, robustness, and usability.
- Support production projects, analyze complex flow issues, drive root-cause analysis, and develop systematic solutions to prevent recurrence.
- Communicate technical strategy, implementation status, risks, and recommendations clearly to engineering stakeholders and leadership.
Qualifications
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
- Strong understanding of ASIC physical design fundamentals, including floorplanning, placement, routing, timing analysis, hierarchical design, and timing closure.
- Experience with full-chip physical design, particularly long-distance interconnect optimization, repeater/buffer insertion, feedthrough planning, or related methodologies.
- Experience with physical design tools such as Cadence Innovus and/or Synopsys Fusion Compiler/ICC2.
- Strong programming and scripting skills in Tcl, Python, Perl.
- Demonstrated experience developing and deploying CAD/EDA methodologies and automation for large-scale SoC designs.
- Proven ability to independently drive complex methodology development from problem definition and solution architecture through implementation, validation, and production deployment.
- Experience providing technical leadership, mentoring engineers, and driving cross-functional technical decisions.
- Excellent debugging and analytical skills with the ability to identify root causes and develop scalable solutions.
- Strong communication skills and demonstrated ability to collaborate with multiple engineering teams.
Skills
Required:Full-chip floorplan methodologyFloorplanning, placement, routing, timing analysisTcl, Python, PerlCAD/EDA methodologies for large-scale SoCsTechnical leadership & mentoringDebugging and root-cause analysisCommunication across engineering teams
Nice to have:Interconnect optimization (long-distance)Cadence Innovus / Synopsys Fusion Compiler / ICC2
Last updated Oct 22, 2026. Interested? Apply on the company site.
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