Sr. Staff Physical Design Engineer
Hybrid (Vancouver, BC), Hybrid (Markham, ON)CA$155.2k - CA$232.8kFull-timePosted 5d ago
About the role
Senior-level physical design engineer role focused on AMD graphics IP for next-generation AI data center chips. Own and drive complex physical design blocks, collaborate across RTL and physical design teams, lead execution, and mentor engineers throughout design closure.
Responsibilities
- Own the physical design of complex, multi-million-gate graphics IP blocks and drive designs toward required performance, power, and area targets.
- Partner with RTL design teams to identify frequency bottlenecks and address logic-level and timing issues early in the project lifecycle.
- Drive floorplanning, power planning, synthesis, placement, clock tree synthesis, routing, extraction, timing closure, and physical verification.
- Perform and support DRC/LVS verification, crosstalk analysis, and EM/IR analysis through final design signoff.
- Establish and improve physical design methodologies for large IP delivery, including IP integration and design-quality checks.
- Drive design optimization for timing, power, area, and design-cycle efficiency.
- Develop and enhance scripts and automated design flows to improve physical design execution.
- Provide technical leadership and mentoring to engineers throughout design closure.
- Collaborate across geographically distributed engineering teams to deliver projects against technical requirements.
Qualifications
- Strong experience in physical design for high-performance semiconductor designs, including timing closure and physical signoff.
- Experience with synthesis and timing-driven place and route of RTL blocks for high-speed datapath and control-logic applications.
- Experience with floorplanning, clock tree synthesis, clock and power gating, scan stitching, routing, extraction, and physical verification.
- Experience with physical design and signoff tools such as Synopsys ICC2, ICC, Fusion Compiler, PrimeTime and StarRC; Mentor Graphics Calibre; Apache RedHawk; and Cadence Innovus and Genus.
- Experience establishing design methodologies, integrating IP, performing logic-equivalence checks, and validating physical, timing, and electrical quality for large IP delivery.
- Experience with advanced process technologies, including N2P or below.
- Proficiency with Python and TCL for design-flow development and automation.
- Experience leading engineers through design closure and providing technical mentorship.
- Familiarity with RTL design, logic-level optimization, and computer organization/architecture.
- Experience applying or developing AI techniques for performance, power, and area optimization is desirable.
- Bachelors or Masters in Electronics/Electrical Engineering preferred.
Skills
Required:Physical design leadershipTiming closureSynthesisFloorplanningPhysical verification
Nice to have:Automation/ scripting
Last updated Oct 22, 2026. Interested? Apply on the company site.
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