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Silicon Photonics Design Engineer

AMD· Engineering
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San Jose, CA$200k - $300kFull-timePosted 5d ago

About the role

Seasoned technical contributor responsible for end-to-end delivery of PIC solutions for optical IO in next-generation AI and HPC applications, interfacing with hardware engineering teams and AMD partners to plan, develop, and optimize silicon photonics solutions.

Responsibilities

  • Development of OE systems in advanced Si photonics process technologies for DWDM and CWDM applications in next generation AI and HPC applications.
  • Innovation, product definition and specification of PIC architectures, TX chains, RX chains, components and test methodologies to meet demanding next generation Optical IO applications.
  • Work with systems teams to devise, maintain, simulate and optimize Optical IO link budgets reflecting key product requirements, PIC architectures, channel properties, active device component and passive component limits as well as foundry process technology capabilities.
  • Collaborate on design-for-test best practices to ensure that photonic devices will be ready for high-volume manufacturing.
  • Participate in design reviews as a subject matter expert in silicon photonic component design.
  • Work cross functionally with EIC, packaging, foundry technology, test development, and product teams to architect appropriate design and test automation solutions.

Qualifications

  • Masters or PhD degree in Applied Physics/Electrical Engineering/or related discipline.
  • Significant success driving photonic PDK, device, & circuit design.
  • Meticulous about DFx and software while driving schedule and managing cost.
  • Subject matter expert and strong technical contributor with PIC theory, design, layout, simulation, packaging, debug, test, manufacturing, reliability, qualification and support.
  • Excellent communication, management, and presentation skills.

Skills

Required:PIC theory, design, layout, simulationDesign-for-test (DFx)Communication and collaboration
Nice to have:PythonCadenceFDTD/MODEPhotonic wafer-, die-, and package-level testing
Last updated Oct 22, 2026. Interested? Apply on the company site.
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