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PMTS - DFT Architect

AMD· Engineering
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Bangalore, IndiaFull-timePosted 5d ago

About the role

DFT Architect role within AMD's Circuit Technologies (CT) Team. You will architect, develop, and lead the DFT Design and Integration of advanced DFT structures (SCAN, ATPG, MBIST, BSCAN), collaborate with SoC/chiplet and IP architects, and drive DFx strategy across debug, test, validation, reliability, and manufacturability from concept to production.

Responsibilities

  • Develop next-generation SoC/chiplet and IP debug and observability solutions that enable secure, scalable, and robust silicon bring-up, validation, and post-silicon debug.
  • Partner with architecture and SoC/chiplet and IP design teams to define and execute a comprehensive Design-for-Excellence (DFX) strategy spanning debug, test, validation, reliability, and manufacturability.
  • Collaborate with technology, silicon validation, product engineering, and manufacturing teams to establish DFX architectures that support both functional operating modes and manufacturing test requirements.
  • Drive cross-functional alignment on DFX requirements, use cases, and end-to-end implementation flows across AMD engineering organizations.
  • Evaluate and deploy AI-driven methodologies to streamline DFX planning, insertion, verification, coverage analysis, and implementation, improving quality, consistency, and scalability while reducing manual effort and time-to-deployment.
  • Define metrics, methodologies, and automation frameworks to ensure DFX solutions meet product quality, testability, debug, and production readiness objectives across multiple programs and technology generations.

Qualifications

  • 10+ years of experience in SoC/chiplet and IP design, DFX architecture, or related silicon development disciplines.
  • Strong understanding of DFX implementation and integration within complex, large-scale SoC/chiplet architectures.
  • Deep knowledge of DFT methodologies and infrastructure, including scan, ATPG, MBIST, JTAG 1149.x/boundary scan, and advanced debug and test features.
  • Solid understanding of SoC clocking, reset, power management, and low-power design architectures.
  • Strong analytical, organizational, and communication skills with the ability to collaborate effectively across diverse engineering teams and disciplines.
  • Demonstrated ability to decompose complex technical problems, evaluate tradeoffs, and develop solutions from both architectural and implementation perspectives.
  • Experience applying AI and data-driven techniques to improve engineering productivity, including DFX requirement analysis, insertion planning, verification, coverage assessment, validation, and design quality optimization.
  • Ability to leverage modern AI-assisted engineering workflows and tools to accelerate debug, reduce manual effort, improve consistency, and enable earlier identification of design and DFX risks.

Skills

Required:DFX architectureDFT methodologies (scan, ATPG, MBIST, JTAG 1149.x)SoC/chiplet and IP designClocking, reset, power management, low-power design
Nice to have:AI/Data-driven engineering productivity

Benefits

  • AMD benefits at a glance.
Last updated Oct 22, 2026. Interested? Apply on the company site.
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