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PD Engineer

AMD· Engineering
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BangaloreFull-timePosted 5d ago

About the role

Physically design high-performance ASIC/SoC blocks from synthesis to tapeout, ensuring timing, power, area, and reliability targets across advanced technology nodes; collaborate with RTL, Synthesis, DFT, STA, Power, and Verification teams and develop automation to improve PD productivity.

Responsibilities

  • Perform physical implementation of digital blocks from netlist to GDSII.
  • Execute and optimize: Floorplanning, Power Planning, Placement, Clock Tree Synthesis (CTS), Routing, Timing Closure, Physical Verification.
  • Analyze and close: Setup and Hold timing violations, Signal Integrity issues, Crosstalk violations, IR Drop and Electromigration (EM), DRC/LVS violations.
  • Work closely with RTL, Synthesis, DFT, STA, Power, and Verification teams.
  • Develop methodologies and automation scripts to improve PD productivity.
  • Support tapeout activities and signoff closure.
  • Debug physical design issues across advanced technology nodes (5nm/3nm/2nm as applicable).

Qualifications

  • Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, VLSI Design, or Computer Engineering

Skills

Required:RTL-to-GDSII implementationFloorplanningPower Grid DesignPlacementClock Tree Synthesis (CTS)RoutingTiming ClosurePhysical Verification (DRC/LVS)DSP/Timing AnalysisScripting
Nice to have:Low Power Design

Benefits

  • AMD benefits at a glance (link provided in description)
Last updated Oct 22, 2026. Interested? Apply on the company site.
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