SoC Physical Integration Engineer
San Jose, CA$166.4kFull-timePosted 5d ago
About the role
AMD SoC Physical Integration Engineer within the Adaptive Embedded Computing Group (AECG) focused on physical and electrical verification, integration, and tape-out of AMD SoC FPGA/ACAP devices for edge computing applications.
Responsibilities
- Define and develop flows and methodologies for chip-level integration.
- Develop tools and automation to enhance design verification and engineering efficiency.
- Design, verify, and integrate FPGA/ACAP sub-blocks, including RTL and custom design.
- Coordinate activities across design teams to enable seamless chip-level integration.
- Execute chip-level physical verification.
- Execute chip-level electrical verification.
Qualifications
- Bachelor’s or Master’s degree in Electrical Engineering or an equivalent field.
- Solid understanding of FPGA architectures.
- Hands-on experience with advanced process nodes, including leading-edge 2nm and 3nm technologies.
- In-depth knowledge of 2.5D and 3D interposer technologies.
- Hands-on experience with physical implementation using industry-standard physical design tools (e.g., Virtuoso, ICC2, Fusion Compiler, Innovus, or comparable tools).
- Strong foundation in circuit design with SPICE and Verilog.
- Knowledge of or practical experience with Place and Route (P&R) tools and methodologies.
- Strong debugging, analytical, and problem-solving skills.
- Proficiency in scripting languages (Perl, Python, TCL, C-shell, Make, or similar).
- Experience with Unix/Linux environments, data management, and job control.
- Excellent written and verbal communication skills for cross-functional collaboration.
Skills
Required:FPGA/ACAP architecturesAdvanced process technologies2.5D/3D interposer technologiesPhysical design toolsCircuit design & simulationPlace and Route (P&R)ScriptingUnix/LinuxCommunication
Benefits
- AMD benefits at a glance
Last updated Oct 22, 2026. Interested? Apply on the company site.
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