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Design Verification Engineer - Power Management (Early Career or Experienced)

Apple· Hardware
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SwindonFull-timePosted 3d ago

About the role

Design Verification Engineer to enable bug-free first silicon for mixed-signal designs, collaborating with Digital and Analog Design engineers. Responsibilities span all pre-silicon verification phases, verification environment development, test planning, and automated verification flows to support RTL release and tape-out.

Responsibilities

  • Establish design verification methodology and test-plan development
  • Verification environment development (stimulus, checkers, test-writing, debug, coverage, sign-off for RTL freeze and tape-out)
  • Develop verification plans in coordination with design leads and architects
  • Build and maintain verification test bench components and environments
  • Generate directed and constrained random tests
  • Run simulations and debug design and environment issues
  • Build functional coverage points, analyze coverage, and improve test environment to target coverage holes
  • Craft automated verification flows for block and chip level verification
  • Apply knowledge of HDL (VHDL/Verilog), hardware verification languages (SystemVerilog/UVM/OVM/VVM), and logic simulators to verify complex designs
  • Collaborate with other block and core level engineers to ensure a flawless verification flow

Qualifications

  • Strong knowledge of SystemVerilog and UVM
  • Experience developing scalable and portable test-benches
  • Experience with constrained random verification environments
  • MS/BS in Computer Science or Electrical Engineering or equivalent
  • Fluency in English language
  • Experience defining coverage space, writing coverage model, analyzing results
  • Experience with Assertion Based Verification
  • Knowledge of Object Oriented Programming
  • Experience in Formal Verification (Formal Linting, Formal connectivity, user property verification)
  • Experience with Python, Perl or TCL
  • Excellent communication and interpersonal skills combined with the ability to collaborate
  • Basic knowledge of mixed signal verification

Skills

Required:SystemVerilogUVMTest bench developmentConstrained random verificationHDL (VHDL/Verilog)Python/Perl/TCL
Nice to have:Formal VerificationObject Oriented Programming
Last updated Oct 23, 2026. Interested? Apply on the company site.

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