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PHY Design Verification Engineer

Apple· Hardware
Apply on company site
Hybrid (San Francisco Bay Area, CA), Hybrid (San Diego, CA), Hybrid (Waltham, MA)$184.7k - $324.8k + equity + bonusFull-timePosted 3d ago

About the role

Responsible for pre-silicon RTL verification of wireless PHY and its interfaces within Apple's wireless SoC. Collaborates with DV methodologists, designers, and systems engineers to develop reusable test benches and verification environments, employing metric-driven verification and AI/ML to enhance DV quality. Supports PHY validation using Palladium/FPGA and contributes to improving DV methodology and flow.

Responsibilities

  • Work closely with the system and design teams to review and understand the PHY subsystem microarchitecture, and create verification plans from specifications, review and refine to achieve coverage targets.
  • Build block/subsystem level test benches with a reference model, using the best-in-class DV methodology. Architect test benches with maximum reusability in mind.
  • Develop and execute both directed and constrained random tests, debug failures, manage bug tracking, and work with designers to drive closure of issues found.
  • Create and analyze block/subsystem-level coverage models, and add test cases to increase coverage.
  • Use machine learning and AI technologies to identify design and test bench issues and ensure DV quality.
  • Support PHY subsystem validation using Palladium and/or FPGA.
  • Work with team members to improve DV methodology and flow.

Qualifications

  • BS and a minimum of 10 years relevant industry experience
  • Verification experience of wireless/wired communication block/subsystem.
  • Advanced knowledge of Verilog, SystemVerilog, UVM, and SystemVerilog Assertion.
  • Excellent knowledge and experience of ASIC verification flows including test bench development, constrained random testing, and code/functional coverage.
  • Experience of using Matlab/C reference model and bit-accurate verification.
  • Verification experience of wireless/wired communication block/subsystem.
  • Knowledge of wireless protocols such as Bluetooth, UWB, WLAN, or Zigbee.
  • Proficient in shell and Python scripting, Perl scripting.
  • Experience of using AI technologies in data mining/analysis.
  • Experience of Palladium/FPGA validation.
  • Should be a team player with excellent communication skills, self-motivated and well organized.

Skills

Required:VerilogSystemVerilog/UVMASIC verification flowsPython scripting
Nice to have:MatlabPalladium/FPGA validationWireless protocolsScripting languages

Benefits

  • Comprehensive medical and dental coverage
  • Retirement benefits
  • Discounted products and free services
  • Reimbursement for certain educational expenses (tuition)
  • Discretionary bonuses or commission payments (eligibility varies)
  • Relocation assistance (if applicable)
Last updated Oct 23, 2026. Interested? Apply on the company site.

About Apple

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