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Design Verification Engineer for Cellular Baseband (m/f/d)

Apple· Hardware
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Hybrid (Munich)Full-timePosted 3d ago

About the role

Design Verification Engineer responsible for verification of high-throughput cellular baseband modems and RF link controllers for Apple’s SOCs, developing reusable UVM verification environments, coverage-driven tests, and adopting ML-based tooling to improve verification efficiency and quality.

Responsibilities

  • Construct detailed test plans for various components of the design including use cases, through collaborative work with multi-functional teams.
  • Create coverage-driven verification plans from specifications; review and refine to achieve coverage targets.
  • Architect UVM-based, reusable test benches with components for stimulus, checkers, VIPs, and reference models.
  • Leverage Large Language Models (LLMs) to enhance verification processes, delivering improvements in efficiency and quality.
  • Design and implement ML-driven workflows that increase team productivity and overall quality of verification.
  • Implement test plans from RTL simulation bring-up to sign-off; report and debug failures.
  • Maintain regressions and report the verification progress against test plans and coverage metrics.

Qualifications

  • Knowledge of SystemVerilog and UVM.
  • Experience with SystemC, C/C++, Python/perl.
  • Ability to develop and establish DV Methodologies.
  • Ability to use LLMs and MCPs.
  • Ability to develop Python-based automation solutions.
  • Understanding of constraint random testing, SVA, Coverage driven verification.
  • Test planning and problem-solving skills.
  • BSc, MSc, or higher degree in Electrical Engineering/Computer Science, Embedded Engineering or similar
  • Experience in C/C++ modeling for design verification.
  • Knowledge of 4G/5G cellular physical layer operation (3GPP).
  • Experience with verification of embedded processor cores.
  • Hands-on verification experience of Bus Fabric, NOC, AHB, AXI, based bus architecture in UVM environment.
  • Knowledge of using LLMs to improve efficiency and quality of verification.
  • Understanding of prompt engineering and LLM workflow optimization.

Skills

Required:SystemVerilogUVMC/C++PythonCoverage-driven verificationDV Methodologies
Nice to have:SystemCSVALLMs in verification
Last updated Oct 23, 2026. Interested? Apply on the company site.

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